Patents by Inventor Hsiao-Chiang Lin

Hsiao-Chiang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145244
    Abstract: A method of patterning an underlying structure includes the following. A first patterning process is performed on the underlying structure to form a first patterned underlying structure including a first opening. A patterned photoresist layer is formed, and the patterned photoresist layer fills the first opening. A second patterning process is performed on the first patterned underlying structure to form a second patterned underlying structure including the first opening and a second opening.
    Type: Application
    Filed: January 17, 2023
    Publication date: May 2, 2024
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Yun-An Chen, Hsiao-Shan Huang, Hsiao-Chiang Lin
  • Patent number: 11143973
    Abstract: A method for designing a photomask includes calculating an open ratio of an initial photomask to determine whether the open ratio of the initial photomask is less than 25%, and then changing a design of the initial photomask in response to determining the open ratio is less than 25%, such that a changed photomask has a reverse tone to the design of the initial photomask, and an open ratio of the changed photomask is 75% or more. The method can solve the issue caused by thermal expansion of the photomask.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: October 12, 2021
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Hsiao-Chiang Lin, Yu-Hsuan Chang, Li-Chun Tseng
  • Patent number: 10854555
    Abstract: A method of manufacturing a mark including the following steps is provided. A substrate including a device area and a mark area is provided. A dielectric layer is formed on the substrate. A dual damascene opening is formed in the dielectric layer of the device area. The dual damascene opening includes a first opening and a second opening connected to each other. The width of the second opening is greater than the width of the first opening. A third opening is formed in the dielectric layer of the mark area. The third opening and the first opening are simultaneously formed by the same process. A barrier material layer is formed on the surfaces of the dual damascene opening and the third opening. The barrier material layer seals the third opening to form a void in the third opening. A metal material layer is formed on the barrier material layer.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: December 1, 2020
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Hsiao-Chiang Lin, Chia-Kuang Lee, Shih-Ci Yen
  • Publication number: 20200241431
    Abstract: A method for designing a photomask includes calculating an open ratio of an initial photomask to determine whether the open ratio of the initial photomask is less than 25%, and then changing a design of the initial photomask in response to determining the open ratio is less than 25%, such that a changed photomask has a reverse tone to the design of the initial photomask, and an open ratio of the changed photomask is 75% or more. The method can solve the issue caused by thermal expansion of the photomask.
    Type: Application
    Filed: April 3, 2019
    Publication date: July 30, 2020
    Applicant: Powerchip Technology Corporation
    Inventors: Hsiao-Chiang Lin, Yu-Hsuan Chang, Li-Chun Tseng
  • Patent number: 9368396
    Abstract: A gap fill treatment for via process is provided. A substrate with a plurality of openings has formed therein is provided. The substrate includes a dense pattern region and an isolated pattern region. A positive resist layer is formed to fill in the openings on the substrate, wherein the thickness of the positive resist layer on the surface of the isolated pattern region is greater than that on the surface of the dense pattern region. The positive resist layer on the surface of the substrate is exposed only. The exposed positive resist layer is developed to form a gap-filling material layer, wherein the gap-filling material layer has the same thickness in the dense pattern region and in the isolated pattern region. A reagent is coated on the surface to form a reaction layer. The reaction layer is removed so that a cap layer remained on the gap-filling material layer.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: June 14, 2016
    Assignee: Powerchip Technology Corporation
    Inventors: Hsiao-Chiang Lin, Kuan-Heng Lin
  • Publication number: 20090311844
    Abstract: An alignment mark, disposed on a substrate, is provided. The alignment mark includes a first dielectric layer and a metal layer. The first dielectric layer is disposed on the substrate and includes an alignment trench and a contact hole. The metal layer is disposed in the alignment trench and the contact hole, wherein a surface of the metal layer is even with a surface of the first dielectric layer. Because the metal layer and the first dielectric layer have different reflection indexes and different refraction indexes, an alignment light detects the alignment mark according to these differences.
    Type: Application
    Filed: June 17, 2008
    Publication date: December 17, 2009
    Applicant: POWERCHIP SEMICONDUCTOR CORP.
    Inventors: Hung-Ming Lin, Hsiao-Chiang Lin, Meng-Feng Tsai, De-An Chiu