Patents by Inventor Hsiao-Chiang Yao
Hsiao-Chiang Yao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10644167Abstract: A thin film transistor including a flexible substrate, a semiconductor layer, a first gate, and a first gate dielectric layer is provided. The semiconductor layer is located on the flexible substrate. The first gate is located on the flexible substrate and corresponds to a portion of the semiconductor layer. The first gate dielectric layer is located between the first gate and the semiconductor layer. The first gate dielectric layer is in contact with the semiconductor layer, and the hydrogen atom concentration of the first gate dielectric layer is less than 6.5×1020 atoms/cm3. A method of manufacturing the thin film transistor is also provided.Type: GrantFiled: March 6, 2018Date of Patent: May 5, 2020Assignees: Industrial Technology Research Institute, Intellectual Property Innovation CorporationInventors: Tai-Jui Wang, Yung-Hui Yeh, Jui-Wen Yang, Hsiao-Chiang Yao, Chun-Hung Chu
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Publication number: 20190140106Abstract: A thin film transistor including a flexible substrate, a semiconductor layer, a first gate, and a first gate dielectric layer is provided. The semiconductor layer is located on the flexible substrate. The first gate is located on the flexible substrate and corresponds to a portion of the semiconductor layer. The first gate dielectric layer is located between the first gate and the semiconductor layer. The first gate dielectric layer is in contact with the semiconductor layer, and the hydrogen atom concentration of the first gate dielectric layer is less than 6.5×1020 atoms/cm3. A method of manufacturing the thin film transistor is also provided.Type: ApplicationFiled: March 6, 2018Publication date: May 9, 2019Applicants: Industrial Technology Research Institute, Intellectual Property Innovation CorporationInventors: Tai-Jui Wang, Yung-Hui Yeh, Jui-Wen Yang, Hsiao-Chiang Yao, Chun-Hung Chu
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Patent number: 10083989Abstract: A semiconductor device is provided to include a flexible substrate, a barrier layer, a heat insulating layer, a device layer, a dielectric material later and a stress absorbing layer. The barrier layer is disposed on the flexible substrate. The heat insulating layer is disposed on the barrier layer, wherein the heat insulating layer has a thermal conductivity of less than 20 W/mK. The device layer is disposed on the heat insulating layer. The dielectric material layer is disposed on the device layer, and the dielectric material layer and the heat insulating layer include at least one trench. The stress absorbing layer is disposed on the dielectric material layer, and the stress absorbing layer fills into the at least one trench.Type: GrantFiled: July 14, 2016Date of Patent: September 25, 2018Assignee: Industrial Technology Research InstituteInventors: Tai-Jui Wang, Tsu-Chiang Chang, Yu-Hua Chung, Wei-Han Chen, Hsiao-Chiang Yao
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Patent number: 9786790Abstract: In one embodiment, a flexible device is provided. The flexible device may include a flexible substrate, a buffer layer, a light reflective layer, and a device layer. The buffer layer is located on the flexible substrate. The light reflective layer is located on the flexible substrate, wherein the light reflective layer has a reflection wavelength of 200 nm˜1100 nm, a reflection ratio of greater than 80%, and a stress direction of the light reflective layer is the same as a stress direction of the flexible substrate. The device layer is located on the light reflective layer and the buffer layer.Type: GrantFiled: March 7, 2016Date of Patent: October 10, 2017Assignee: Industrial Technology Research InstituteInventors: Ching-Wen Su, Tai-Jui Wang, Hsiao-Chiang Yao, Tsu-Chiang Chang, Bo-Yuan Su
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Publication number: 20170170329Abstract: In one embodiment, a flexible device is provided. The flexible device may include a flexible substrate, a buffer layer, a light reflective layer, and a device layer. The buffer layer is located on the flexible substrate. The light reflective layer is located on the flexible substrate, wherein the light reflective layer has a reflection wavelength of 200 nm˜1100 nm, a reflection ratio of greater than 80%, and a stress direction of the light reflective layer is the same as a stress direction of the flexible substrate. The device layer is located on the light reflective layer and the buffer layer.Type: ApplicationFiled: March 7, 2016Publication date: June 15, 2017Inventors: Ching-Wen Su, Tai-Jui Wang, Hsiao-Chiang Yao, Tsu-Chiang Chang, Bo-Yuan Su
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Publication number: 20170170207Abstract: A semiconductor device is provided to include a flexible substrate, a barrier layer, a heat insulating layer, a device layer, a dielectric material later and a stress absorbing layer. The barrier layer is disposed on the flexible substrate. The heat insulating layer is disposed on the barrier layer, wherein the heat insulating layer has a thermal conductivity of less than 20 W/mK. The device layer is disposed on the heat insulating layer. The dielectric material layer is disposed on the device layer, and the dielectric material layer and the heat insulating layer include at least one trench. The stress absorbing layer is disposed on the dielectric material layer, and the stress absorbing layer fills into the at least one trench.Type: ApplicationFiled: July 14, 2016Publication date: June 15, 2017Inventors: Tai-Jui Wang, Tsu-Chiang Chang, Yu-Hua Chung, Wei-Han Chen, Hsiao-Chiang Yao
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Patent number: 9553176Abstract: A semiconductor device includes a gate, a first electrode, a first insulating layer, an active layer, an etching stop layer, a second insulating layer, a source, a drain and a second electrode. The first insulating layer covers the gate and the first electrode. The active layer and the etching stop layer are disposed on the first insulating layer above the gate and the first electrode respectively. The second insulating layer covers the active layer and the etching stop layer and has a first opening and a second opening exposing the active layer and a third opening exposing the etching stop layer. The source and the drain are disposed on the second insulating layer and contact with the active layer through the first opening and the second opening respectively. The second electrode is located on the second insulating layer and contacts with the etching stop layer through the third opening.Type: GrantFiled: September 9, 2015Date of Patent: January 24, 2017Assignee: Industrial Technology Research InstituteInventors: Jing-Yi Yan, Chih-Chieh Hsu, Hsiao-Chiang Yao, Chu-Yin Hung
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Publication number: 20150380530Abstract: A semiconductor device includes a gate, a first electrode, a first insulating layer, an active layer, an etching stop layer, a second insulating layer, a source, a drain and a second electrode. The first insulating layer covers the gate and the first electrode. The active layer and the etching stop layer are disposed on the first insulating layer above the gate and the first electrode respectively. The second insulating layer covers the active layer and the etching stop layer and has a first opening and a second opening exposing the active layer and a third opening exposing the etching stop layer. The source and the drain are disposed on the second insulating layer and contact with the active layer through the first opening and the second opening respectively. The second electrode is located on the second insulating layer and contacts with the etching stop layer through the third opening.Type: ApplicationFiled: September 9, 2015Publication date: December 31, 2015Inventors: Jing-Yi Yan, Chih-Chieh Hsu, Hsiao-Chiang Yao, Chu-Yin Hung
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Patent number: 9165947Abstract: A semiconductor device includes a gate, a first electrode, a first insulating layer, an active layer, an etching stop layer, a second insulating layer, a source, a drain and a second electrode. The first insulating layer covers the gate and the first electrode. The active layer and the etching stop layer are disposed on the first insulating layer above the gate and the first electrode respectively. The second insulating layer covers the active layer and the etching stop layer and has a first opening and a second opening exposing the active layer and a third opening exposing the etching stop layer. The source and the drain are disposed on the second insulating layer and contact with the active layer through the first opening and the second opening respectively. The second electrode is located on the second insulating layer and contacts with the etching stop layer through the third opening.Type: GrantFiled: March 23, 2012Date of Patent: October 20, 2015Assignee: Industrial Technology Research InstituteInventors: Jing-Yi Yan, Chih-Chieh Hsu, Hsiao-Chiang Yao, Chu-Yin Hung
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Patent number: 8928046Abstract: A transistor including a gate, an active stacked structure, a dielectric layer, a source and a drain. The gate is located over a first surface of the dielectric layer. The active stacked structure, including a first active layer and a second active layer, is located over a second surface of the dielectric layer. The source and the drain are located over the second surface of the dielectric layer and at two sides of the active stacked structure and extend between the first active layer and the second active layer of the active stacked structure.Type: GrantFiled: October 13, 2010Date of Patent: January 6, 2015Assignee: Industrial Technology Research InstituteInventors: Jing-Yi Yan, Chu-Yin Hung, Hsiao-Chiang Yao, Yen-Yu Wu, Yen-Shih Huang
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Publication number: 20140217400Abstract: A semiconductor element structure and a manufacturing method for the same are provided. The semiconductor element structure may comprise a gate electrode, a dielectric layer, an active layer, a source, a drain and a protective layer. The active layer and the gate electrode are disposed on opposing sides of the dielectric layer. The source is disposed on the active layer. The drain is disposed on the active layer. The protective layer is disposed on the active layer. The protective layer may have a hydrogen content less than or equal to 0.1 at % and a sheet resistance higher than or equal to 10? 10 Ohm/sq.Type: ApplicationFiled: January 31, 2014Publication date: August 7, 2014Applicant: Industrial Technology Research InstituteInventors: Jing-Yi YAN, Chu-Yin HUNG, Liang-Hsiang CHEN, Hsiao-Chiang YAO, Wu-Wei TSAI
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Publication number: 20130140635Abstract: A semiconductor device includes a gate, a first electrode, a first insulating layer, an active layer, an etching stop layer, a second insulating layer, a source, a drain and a second electrode. The first insulating layer covers the gate and the first electrode. The active layer and the etching stop layer are disposed on the first insulating layer above the gate and the first electrode respectively. The second insulating layer covers the active layer and the etching stop layer and has a first opening and a second opening exposing the active layer and a third opening exposing the etching stop layer. The source and the drain are disposed on the second insulating layer and contact with the active layer through the first opening and the second opening respectively. The second electrode is located on the second insulating layer and contacts with the etching stop layer through the third opening.Type: ApplicationFiled: March 23, 2012Publication date: June 6, 2013Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Jing-Yi Yan, Chih-Chieh Hsu, Hsiao-Chiang Yao, Chu-Yin Hung
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Publication number: 20110254061Abstract: A transistor including a gate, an active stacked structure, a dielectric layer, a source and a drain. The gate is located over a first surface of the dielectric layer. The active stacked structure, including a first active layer and a second active layer, is located over a second surface of the dielectric layer. The source and the drain are located over the second surface of the dielectric layer and at two sides of the active stacked structure and extend between the first active layer and the second active layer of the active stacked structure.Type: ApplicationFiled: October 13, 2010Publication date: October 20, 2011Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Jing-Yi Yan, Chu-Yin Hung, Hsiao-Chiang Yao, Yen-Yu Wu, Yen-Shih Huang