Patents by Inventor Hsiao-Ching Huang

Hsiao-Ching Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12364023
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a first semiconductor device and second semiconductor device disposed on a semiconductor substrate. The first semiconductor device comprises a first gate structure, a first source region, and a first drain region. The first source and drain regions and are disposed in a first well region. The second semiconductor device comprises a second gate structure, a second source region, and a second drain region. The second source and drain regions are disposed in a second well region. The first and second well regions comprise a first doping type. The first well region is laterally offset from the second well region by a first distance. A third well region is disposed in the semiconductor substrate and laterally between the first and second well regions. The third well region comprises a second doping type opposite the first doping type.
    Type: Grant
    Filed: June 3, 2022
    Date of Patent: July 15, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Ching Huang, Hao-Hua Hsu, Sheng-Fu Hsu
  • Publication number: 20240371858
    Abstract: The ability of a grounded gate NMOS (ggNMOS) device to withstand and protect against human body model (HBM) electrostatic discharge (ESD) events is greatly increased by resistance balancing straps. The resistance balancing straps are areas of high resistance formed in the substrate between an active area that includes a MOSFET of the ggNMOS device and a bulk ring that surrounds the active area. A Vss rail is coupled to the substrate beneath the MOSFET through the bulk ring. The substrate beneath the MOSFET provides base regions for parasitic transistors that switch on for the ggNMOS device to operate. The straps inhibit low resistance pathways between the base regions and the bulk ring and prevent a large portion of the ggNMOS device from being switched off while a remaining portion of the ggNMOS device remains switched on. The strap may be divided into segments inserted at strategic locations.
    Type: Application
    Filed: July 19, 2024
    Publication date: November 7, 2024
    Inventors: Hsiao-Ching Huang, Sheng-Fu Hsu, Hao-Hua Hsu, Pin-Chen Chen, Lin-Yu Huang, Yu-Chang Jong
  • Patent number: 12132042
    Abstract: The ability of a grounded gate NMOS (ggNMOS) device to withstand and protect against human body model (HBM) electrostatic discharge (ESD) events is greatly increased by resistance balancing straps. The resistance balancing straps are areas of high resistance formed in the substrate between an active area that includes a MOSFET of the ggNMOS device and a bulk ring that surrounds the active area. A Vss rail is coupled to the substrate beneath the MOSFET through the bulk ring. The substrate beneath the MOSFET provides base regions for parasitic transistors that switch on for the ggNMOS device to operate. The straps inhibit low resistance pathways between the base regions and the bulk ring and prevent a large portion of the ggNMOS device from being switched off while a remaining portion of the ggNMOS device remains switched on. The strap may be divided into segments inserted at strategic locations.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: October 29, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Ching Huang, Sheng-Fu Hsu, Hao-Hua Hsu, Pin-Chen Chen, Lin-Yu Huang, Yu-Chang Jong
  • Publication number: 20240030215
    Abstract: The ability of a grounded gate NMOS (ggNMOS) device to withstand and protect against human body model (HBM) electrostatic discharge (ESD) events is greatly increased by resistance balancing straps. The resistance balancing straps are areas of high resistance formed in the substrate between an active area that includes a MOSFET of the ggNMOS device and a bulk ring that surrounds the active area. A Vss rail is coupled to the substrate beneath the MOSFET through the bulk ring. The substrate beneath the MOSFET provides base regions for parasitic transistors that switch on for the ggNMOS device to operate. The straps inhibit low resistance pathways between the base regions and the bulk ring and prevent a large portion of the ggNMOS device from being switched off while a remaining portion of the ggNMOS device remains switched on. The strap may be divided into segments inserted at strategic locations.
    Type: Application
    Filed: July 25, 2022
    Publication date: January 25, 2024
    Inventors: Hsiao-Ching Huang, Sheng-Fu Hsu, Hao-Hua Hsu, Pin-Chen Chen, Lin-Yu Huang, Yu-Chang Jong
  • Publication number: 20230395592
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a first semiconductor device and second semiconductor device disposed on a semiconductor substrate. The first semiconductor device comprises a first gate structure, a first source region, and a first drain region. The first source and drain regions and are disposed in a first well region. The second semiconductor device comprises a second gate structure, a second source region, and a second drain region. The second source and drain regions are disposed in a second well region. The first and second well regions comprise a first doping type. The first well region is laterally offset from the second well region by a first distance. A third well region is disposed in the semiconductor substrate and laterally between the first and second well regions. The third well region comprises a second doping type opposite the first doping type.
    Type: Application
    Filed: June 3, 2022
    Publication date: December 7, 2023
    Inventors: Hsiao-Ching Huang, Hao-Hua Hsu, Sheng-Fu Hsu
  • Patent number: 11804482
    Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate of a first type, a first doped region embedded within the substrate and having a first portion and a second portion, and a first gate electrode disposed above the substrate. The semiconductor device further comprises a well region of a second type and embedded within the substrate. The well region is in contact with the second portion of the first doped region.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: October 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Sheng-Fu Hsu, Hsiao-Ching Huang
  • Publication number: 20220102337
    Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate of a first type, a first doped region embedded within the substrate and having a first portion and a second portion, and a first gate electrode disposed above the substrate. The semiconductor device further comprises a well region of a second type and embedded within the substrate. The well region is in contact with the second portion of the first doped region.
    Type: Application
    Filed: September 29, 2020
    Publication date: March 31, 2022
    Inventors: SHENG-FU HSU, HSIAO-CHING HUANG
  • Patent number: D501043
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: January 18, 2005
    Assignee: Hunter Fan Company
    Inventors: Ted E. Bacon, Brian S. Sibson, Hsiao-ching Huang
  • Patent number: D505196
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: May 17, 2005
    Assignee: Hunter Fan Company
    Inventors: Ted E. Bacon, Brian S. Sibson, Hsiao-ching Huang
  • Patent number: D514693
    Type: Grant
    Filed: December 14, 2004
    Date of Patent: February 7, 2006
    Assignee: Hunter Fan Company
    Inventor: Hsiao-ching Huang
  • Patent number: D536431
    Type: Grant
    Filed: July 18, 2005
    Date of Patent: February 6, 2007
    Assignee: Hunter Fan Company
    Inventors: Glennbruce S. Campbell, Hsiao-ching Huang
  • Patent number: D548314
    Type: Grant
    Filed: March 2, 2006
    Date of Patent: August 7, 2007
    Assignee: Hunter Fan Company
    Inventor: Hsiao-ching Huang
  • Patent number: D482439
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: November 18, 2003
    Assignee: Hunter Fan Company
    Inventor: Hsiao-ching Huang
  • Patent number: D484967
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: January 6, 2004
    Assignee: Hunter Fan Company
    Inventor: Hsiao-ching Huang
  • Patent number: D484968
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: January 6, 2004
    Assignee: Hunter Fan Company
    Inventor: Hsiao-ching Huang
  • Patent number: D488554
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: April 13, 2004
    Assignee: Hunter Fan Company
    Inventors: Ted E. Bacon, Brian S. Sibson, Hsiao-ching Huang
  • Patent number: D488555
    Type: Grant
    Filed: July 8, 2003
    Date of Patent: April 13, 2004
    Assignee: Hunter Fan Company
    Inventor: Hsiao-ching Huang
  • Patent number: D489471
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: May 4, 2004
    Assignee: Hunter Fan Company
    Inventor: Hsiao-ching Huang
  • Patent number: D489812
    Type: Grant
    Filed: July 22, 2003
    Date of Patent: May 11, 2004
    Assignee: Hunter Fan Company
    Inventor: Hsiao-ching Huang
  • Patent number: D490148
    Type: Grant
    Filed: July 2, 2002
    Date of Patent: May 18, 2004
    Assignee: Hunter Fan Company
    Inventor: Hsiao-ching Huang