Abstract: Middle-of-line (MOL) interconnects and corresponding techniques for forming the MOL interconnects are disclosed herein. An exemplary MOL interconnect structure includes a barrier-free source/drain contact, a barrier-free source/drain via, and a barrier-free gate via disposed in an insulator layer. The barrier-free source/drain is disposed on an epitaxial source/drain, and the barrier-free source/drain contact includes tungsten, molybdenum, or a combination thereof. The barrier-free source/drain via is disposed on the barrier-free source/drain contact and the barrier-free source/drain via includes molybdenum. The barrier-free gate via is disposed on a gate stack disposed adjacent to the epitaxial source/drain, and the barrier-free gate via includes tungsten, molybdenum, or a combination thereof. A width of the barrier-free source/drain via and/or the barrier-free gate via may be less than about 16 nm. The barrier-free source/drain via and/or the barrier-free gate via may be formed at the same time (e.g.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack over a substrate. The first gate stack includes a first gate electrode and a dielectric layer between the first gate electrode and the substrate, and the first gate electrode has a void. The method includes oxidizing a side portion of the first gate electrode to form an oxide layer over the first gate electrode. The oxide layer fills the void.

Abstract: A device includes a semiconductor fin, a gate dielectric on sidewalls of the semiconductor fin, a gate electrode over the gate dielectric, and isolation regions. The isolation regions include a first portion on a side of the semiconductor fin, wherein the first portion is underlying and aligned to a portion of the gate electrode. The semiconductor fin is over a first top surface of the first portion of the isolation regions. The isolation regions further include second portions on opposite sides of the portion of the gate electrode. The second top surfaces of the second portions of the isolation regions are higher than the first top surface of the isolation regions.

Abstract: A device includes a substrate, an isolation region at a top surface of the substrate, and a semiconductor fin over the isolation region. The semiconductor fin has a fin height smaller than about 400 ?, wherein the fin height is measured from a top surface of the semiconductor fin to a top surface of the isolation region.

Abstract: A device includes a substrate, an isolation region at a top surface of the substrate, and a semiconductor fin over the isolation region.

Abstract: A device includes a substrate, an isolation region at a top surface of the substrate, and a semiconductor fin over the isolation region. The semiconductor fin has a fin height smaller than about 400 ?, wherein the fin height is measured from a top surface of the semiconductor fin to a top surface of the isolation region.

Abstract: System and method for forming lightly doped drain (LDD) extensions. An embodiment comprises forming a gate electrode on a semiconductor fin and forming a dielectric layer over the gate electrode. The gate electrode is then etched to expose a portion of the semiconductor fin. The exposed portions of the fin comprise the LDD extensions.

Abstract: A device includes a substrate, an isolation region at a top surface of the substrate, and a semiconductor fin over the isolation region.

Abstract: A device includes a substrate, an isolation region at a top surface of the substrate, and a semiconductor fin over the isolation region. The semiconductor fin has a fin height smaller than about 400 ?, wherein the fin height is measured from a top surface of the semiconductor fin to a top surface of the isolation region.

Abstract: System and method for forming lightly doped drain (LDD) extensions. An embodiment comprises forming a gate electrode on a semiconductor fin and forming a dielectric layer over the gate electrode. The gate electrode is then etched to expose a portion of the semiconductor fin. The exposed portions of the fin comprise the LDD extensions.

Abstract: A device includes a semiconductor fin, a gate dielectric on sidewalls of the semiconductor fin, a gate electrode over the gate dielectric, and isolation regions. The isolation regions include a first portion on a side of the semiconductor fin, wherein the first portion is underlying and aligned to a portion of the gate electrode. The semiconductor fin is over a first top surface of the first portion of the isolation regions. The isolation regions further include second portions on opposite sides of the portion of the gate electrode. The second top surfaces of the second portions of the isolation regions are higher than the first top surface of the isolation regions.

Abstract: A device includes a substrate, an isolation region at a top surface of the substrate, and a semiconductor fin over the isolation region.