Abstract: In a method of manufacturing a semiconductor device including a Fin FET, a fin structure, which has an upper fin structure made of SiGe and a bottom fin structure made of a different material than the upper fin structure, is formed, a cover layer is formed over the fin structure, a thermal operation is performed on the fin structure covered by the cover layer, and a source/drain epitaxial layer is formed in a source/drain region of the upper fin structure. The thermal operation changes a germanium distribution in the upper fin structure.

Abstract: The present disclosure provides a ball tracking system and method. The ball tracking system includes camera device and processing device. The camera device is configured to generate a plurality of video frame data, wherein the video frame data includes image of ball. The processing device is electrically coupled to the camera device and is configured to: recognize the image of the ball from the plurality of video frame data to obtain 2D estimation coordinate of the ball at first frame time and utilize 2D to 3D matrix to convert the 2D estimation coordinate into first 3D estimation coordinate; utilize model to calculate second 3D estimation coordinate of the ball at the first frame time; and calibrate according to the first 3D estimation coordinate and the second 3D estimation coordinate to generate 3D calibration coordinate of the ball at the first frame time.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over a first portion of the fin structure, and an epitaxial region formed in a second portion of the fin structure. The epitaxial region can include a first semiconductor layer and an n-type second semiconductor layer formed over the first semiconductor layer. A lattice constant of the first semiconductor layer can be greater than that of the second semiconductor layer.

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a fin region formed on a substrate, wherein the fin region includes multiple channels vertically stacked on the substrate; a gate stack disposed on the fin region, wherein the gate stack is wrapping around each of the multiple channels and includes gate extensions being extending laterally to be overlapped with inner spacers; and a pair of source/drain (S/D) features formed the fin region, interposed by the gate stack, and connected with the multiple channels.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over a first portion of the fin structure, and an epitaxial region formed in a second portion of the fin structure. The epitaxial region can include a first semiconductor layer and an n-type second semiconductor layer formed over the first semiconductor layer. A lattice constant of the first semiconductor layer can be greater than that of the second semiconductor layer.

Abstract: The present disclosure describes a semiconductor device with modulated gate structures and a method for forming the same. The method includes forming a fin structure, depositing a polysilicon layer over the fin structure, and forming a photoresist mask layer on the polysilicon layer. The method further includes etching, with a first etching condition, the polysilicon layer not covered by the photoresist mask layer and above a top surface of the fin structure. The method further includes etching, with a second etching condition, the polysilicon layer not covered by the photoresist mask layer and below the top surface of the fin structure, where the etched polysilicon layer below the top surface of the fin structure is narrower than the etched polysilicon layer above the top surface of the fin structure. The method further includes removing the etched polysilicon layer to form a space and forming a gate structure in the space.

Abstract: GAAFET threshold voltages are tuned by introducing dopants into a channel region. In a GAAFET that has a stacked channel structure, dopants can be introduced into multiple channels by first doping nano-structured layers adjacent to the channels. Then, by an anneal operation, dopants can be driven, from surfaces of the doped layers into the channels, to achieve a graduated dopant concentration profile. Following the anneal operation and after the dopants are diffused into the channels, depleted doped layers can be replaced with a gate structure to provide radial control of current in the surface-doped channels.

Abstract: The present disclosure describes a semiconductor device with counter-doped nanostructures and a method for forming the semiconductor device. The method includes forming a fin structure on a substrate, the fin structure including one or more first-type nanostructures and one or more second-type nanostructures. The method further includes forming a polysilicon structure over the fin structure and forming a source/drain (S/D) region on a portion of the fin structure and adjacent the polysilicon structure, the S/D region including a first dopant. The method further includes doping the one or more second-type nanostructures with a second dopant via a space released by the polysilicon structure and the one or more first-type nanostructures, where the second dopant is opposite to the first dopant. The method further includes replacing portions of the one or more doped second-type nanostructures with additional second-type nanostructures.

Abstract: The present disclosure describes semiconductor devices and methods for forming the same. A semiconductor device includes nanostructures over a substrate and a source/drain region in contact with the nanostructures. The source/drain region is doped with a first-type dopant. The semiconductor device also includes a counter-doped structure in contact with the substrate and the source/drain region. The counter-doped structure is doped with a second-type dopant opposite to the first-type dopant.

Abstract: The present disclosure describes a semiconductor device having a buried gate structure. The semiconductor device includes a substrate and a fin structure on the substrate. The fin structure includes a top portion and a bottom portion. The semiconductor device further includes a gate structure on the bottom portion of the fin structure. Multiple semiconductor layers in the top portion of the fin structure are disposed on the gate structure. The semiconductor device further includes a source/drain structure above the gate structure and in contact with the multiple semiconductor layers.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over a first portion of the fin structure, and an epitaxial region formed in a second portion of the fin structure. The epitaxial region can include a first semiconductor layer and an n-type second semiconductor layer formed over the first semiconductor layer. A lattice constant of the first semiconductor layer can be greater than that of the second semiconductor layer.

Abstract: In a method of manufacturing a semiconductor device including a Fin FET, a fin structure, which has an upper fin structure made of SiGe and a bottom fin structure made of a different material than the upper fin structure, is formed, a cover layer is formed over the fin structure, a thermal operation is performed on the fin structure covered by the cover layer, and a source/drain epitaxial layer is formed in a source/drain region of the upper fin structure. The thermal operation changes a germanium distribution in the upper fin structure.

Abstract: A method of manufacturing a semiconductor device includes disposing two or more fins each having an initial fin profile on a substrate. A sacrificial oxide layer is grown on a first fin and a second fin of the two or more fins. The sacrificial oxide layer of the first and second fins is etched to trim the fin and to generate a next fin profile for the first and second fins. The growing and etching is repeated to trim the first and second fins such that the number of repetitions for the first fin and the second fin are different. Gate structures are formed over the two or more fins.

Abstract: A method of forming a semiconductor device includes following steps. A semiconductor strip is formed extending above a semiconductor substrate. A shallow trench isolation (STI) region is formed over the semiconductor substrate. The semiconductor strip has a fin structure higher than a top surface of the STI region. The fin structure includes a channel portion and a source/drain (S/D) portion adjacent to the channel portion. A dummy gate stack is formed over the channel portion. The S/D portion is exposed by the dummy gate stack. A doping process is performed to a top of the S/D portion using first dopants. An epitaxy layer is formed around the top of the S/D portion. The epitaxy layer has second dopants. A conductivity type of the second dopants is different from a conductivity type of the first dopants. The dummy gate stack is replaced with a replacement gate stack.

Abstract: In a method of manufacturing a semiconductor device including a Fin FET, a fin structure, which has an upper fin structure made of SiGe and a bottom fin structure made of a different material than the upper fin structure, is formed, a cover layer is formed over the fin structure, a thermal operation is performed on the fin structure covered by the cover layer, and a source/drain epitaxial layer is formed in a source/drain region of the upper fin structure. The thermal operation changes a germanium distribution in the upper fin structure.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over a first portion of the fin structure, and an epitaxial region formed in a second portion of the fin structure. The epitaxial region can include a first semiconductor layer and an n-type second semiconductor layer formed over the first semiconductor layer. A lattice constant of the first semiconductor layer can be greater than that of the second semiconductor layer.

Abstract: A method of manufacturing a semiconductor device includes disposing two or more fins each having an initial fin profile on a substrate. A sacrificial oxide layer is grown on a first fin and a second fin of the two or more fins. The sacrificial oxide layer of the first and second fins is etched to trim the fin and to generate a next fin profile for the first and second fins. The growing and etching is repeated to trim the first and second fins such that the number of repetitions for the first fin and the second fin are different. Gate structures are formed over the two or more fins.

Abstract: A method of forming a semiconductor device includes following steps. A semiconductor strip is formed extending above a semiconductor substrate. A shallow trench isolation (STI) region is formed over the semiconductor substrate. The semiconductor strip has a fin structure higher than a top surface of the STI region. The fin structure includes a channel portion and a source/drain (S/D) portion adjacent to the channel portion. A dummy gate stack is formed over the channel portion. The S/D portion is exposed by the dummy gate stack. A doping process is performed to a top of the S/D portion using first dopants. An epitaxy layer is formed around the top of the S/D portion. The epitaxy layer has second dopants. A conductivity type of the second dopants is different from a conductivity type of the first dopants. The dummy gate stack is replaced with a replacement gate stack.

Abstract: In a method of manufacturing a semiconductor device including a Fin FET, a fin structure, which has an upper fin structure made of SiGe and a bottom fin structure made of a different material than the upper fin structure, is formed, a cover layer is formed over the fin structure, a thermal operation is performed on the fin structure covered by the cover layer, and a source/drain epitaxial layer is formed in a source/drain region of the upper fin structure. The thermal operation changes a germanium distribution in the upper fin structure.

Abstract: A method of manufacturing a semiconductor device includes disposing two or more fins each having an initial fin profile on a substrate. A sacrificial oxide layer is grown on a first fin and a second fin of the two or more fins. The sacrificial oxide layer of the first and second fins is etched to trim the fin and to generate a next fin profile for the first and second fins. The growing and etching is repeated to trim the first and second fins such that the number of repetitions for the first fin and the second fin are different. Gate structures are formed over the two or more fins.