Abstract: An electronic packaging structure is provided, including a circuit portion, an electronic element disposed on an upper side of the circuit portion and a glass carrier disposed on a lower side of the circuit portion. By replacing a conventional silicon wafer with the glass carrier, the present invention eliminates the need of an adhesive layer and allows quick removal of the glass carrier during a subsequent process, thus saving the fabrication time and increasing the product yield. The present invention further provides a method for fabricating an electronic package.

Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a base portion having at least an electronic element embedded therein and at least a positioning unit formed around a periphery of the electronic element, wherein the positioning unit protrudes from or is flush with a surface of the base portion; and forming at least a circuit layer on the surface of the base portion and the electronic element. The circuit layer is aligned and connected to the electronic element through the positioning unit.

Abstract: An interconnection structure for a package is disclosed. The interconnection structure includes a substrate body having a conductive portion formed on a surface thereof; a first photosensitive dielectric layer formed on the surface of the substrate body and having a via for exposing the conductive potion; a conductive via formed in the via; a second photosensitive dielectric layer formed on the first photosensitive dielectric layer and having a opening for exposing the conductive via and a portion of the first photosensitive dielectric layer; and a conductive trace layer formed in the opening of the second photosensitive dielectric layer so as to be electrically connected to the conductive portion through the conductive via, thereby simplifying the fabrication process and reducing the fabrication cost and time.

Abstract: An interconnection structure for a package is disclosed. The interconnection structure includes a substrate body having a conductive portion formed on a surface thereof; a first photosensitive dielectric layer formed on the surface of the substrate body and having a via for exposing the conductive potion; a conductive via formed in the via; a second photosensitive dielectric layer formed on the first photosensitive dielectric layer and having a opening for exposing the conductive via and a portion of the first photosensitive dielectric layer; and a conductive trace layer formed in the opening of the second photosensitive dielectric layer so as to be electrically connected to the conductive portion through the conductive via, thereby simplifying the fabrication process and reducing the fabrication cost and time.

Abstract: A method for manufacturing a hollowed printed circuit board includes steps of: providing an electrically conductive layer; laminating a first dielectric layer having a first through opening defined therein on a first surface of the electrically conductive layer; forming a protecting layer on the first surface of the electrically conductive layer in the first opening; creating an electrically conductive pattern in the conductive layer; removing the protecting layer; and laminating a second dielectric layer having a second through opening defined therein on an opposite second surface of the electrically conductive layer in a manner that the first through opening is aligned with the second through opening, thereby a portion of the electrically conductive layer is exposed to exterior through the first through opening and the second through opening.

Abstract: An exemplary legend printing stencil for printing a circuit substrate for manufacturing a number of printed circuit board is provided. The stencil includes at least a first printing portion, at least a second printing portion and a junction portion between the first printing portion and the second printing portion. The first printing portion and the second printing portion each define a number of legend holes therein. The first printing portion and the second portion are configured for attaching on and covering the corresponding circuit board unit of the circuit substrate to print legends on the circuit board unit. The junction portion defines a slot therein and is configured for attaching on and covering the corresponding connection portion of the circuit substrate to print a legend ink layer on the connection portion. A method for manufacturing a number of printed circuit boards using the stencil is also provided.

Abstract: A method for manufacturing a hollowed printed circuit board includes steps of: providing an electrically conductive layer; laminating a first dielectric layer having a first through opening defined therein on a first surface of the electrically conductive layer; forming a protecting layer on the first surface of the electrically conductive layer in the first opening; creating an electrically conductive pattern in the conductive layer; removing the protecting layer; and laminating a second dielectric layer having a second through opening defined therein on an opposite second surface of the electrically conductive layer in a manner that the first through opening is aligned with the second through opening, thereby a portion of the electrically conductive layer is exposed to exterior through the first through opening and the second through opening.

Abstract: An exemplary legend printing stencil for printing a circuit substrate for manufacturing a number of printed circuit board is provided. The stencil includes at least a first printing portion, at least a second printing portion and a junction portion between the first printing portion and the second printing portion. The first printing portion and the second printing portion each define a number of legend holes therein. The first printing portion and the second portion are configured for attaching on and covering the corresponding circuit board unit of the circuit substrate to print legends on the circuit board unit. The junction portion defines a slot therein and is configured for attaching on and covering the corresponding connection portion of the circuit substrate to print a legend ink layer on the connection portion. A method for manufacturing a number of printed circuit boards using the stencil is also provided.

Abstract: A method of analyzing accelerator of copper electroplating includes a selective adsorption step and an electrochemical deposition step. First, a gold electrode is placed into a plating solution, which contains organic additives. Then, the gold electrode is dipped in the plating solution for a while to adsorb the sulfur-containing accelerators. After the sulfur-containing accelerators are adsorbed on the gold electrode, the gold electrode is rinsed with Milli-Q ultra pure water. Then, the gold electrode is put into an electrolyte, which contains PEG and chloride ions to carry out a cathodic cyclic voltammetry (CCV) for copper deposition on the gold electrode. A calibration curve for the accelerator analysis can be obtained by integrating the polarization curve measured from the CCV.