Abstract: A semiconductor structure includes a first gate structure, a second gate structure coupled to the first gate structure, a source region, a first drain region, and a second drain region. The source region is surrounded by the first gate structure and the second gate structure. The first drain region is separated from the source region by the first gate structure. The second drain region is separated from the source region by the second gat structure. A shape of the first drain region and a shape of the second drain region are different from each other from a plan view.

Abstract: A dyeing method for functional contact lenses includes the following steps: providing a dry lens body, including hydrogel with 0-90% water content, silicone hydrogel with 0-90% water content, or a combination thereof; preparing an amphoteric polymethyl ether prepolymer, combining the amphoteric polymethyl ether prepolymer with a hydrophilic monomer to form a masking ring material, and attaching the masking ring material to an inner surface of the dry lens body to form a masking ring layer; dropping a colorant onto the inner surface, making the masking ring layer surround the colorant, irradiating the colorant with an ultraviolet light and then heating and fixing the colorant to form a dyed layer on the inner surface; and placing the dry lens body in water to hydrate and removing the masking ring layer to obtain a wet lens body.

Abstract: A semiconductor structure includes a gate structure, a source region, a drain region, and an isolation structure. The gate structure includes a first portion, a second portion and a third portion. The first portion extends in a first direction, and the second portion and the third portion extend in a second direction. The second portion and the third portion are disposed at opposite ends of the first portion. The source region and the drain region are separated by the gate structure. The isolation structure surrounds the gate structure, the source region and the drain region. The first portion has a first sidewall, the second portion has a second sidewall, and the third portion has a third sidewall. The first sidewall, the second sidewall and the third sidewall are parallel to the first direction and aligned with each other to form a straight line.

Abstract: A semiconductor structure includes a gate structure, a source region, a drain region, and an isolation structure. The gate structure includes a first portion, a second portion and a third portion. The first portion extends in a first direction, and the second portion and the third portion extend in a second direction. The second portion and the third portion are disposed at opposite ends of the first portion. The source region and the drain region are separated by the gate structure. The isolation structure surrounds the gate structure, the source region and the drain region. The first portion has a first sidewall, the second portion has a second sidewall, and the third portion has a third sidewall. The first sidewall, the second sidewall and the third sidewall are parallel to the first direction and aligned with each other to form a straight line.

Abstract: According to an exemplary embodiment, a semiconductor device is provided. The semiconductor device includes a first seal ring and a first circuit. The first circuit includes a first capacitor and a first inductor connected in series. The first circuit is connected between the first seal ring and a ground.

Abstract: According to an exemplary embodiment, a semiconductor device is provided. The semiconductor device includes a first seal ring and a first circuit. The first circuit includes a first capacitor and a first inductor connected in series. The first circuit is connected between the first seal ring and a ground.

Abstract: A semiconductor device includes a substrate and a through substrate via structure. The substrate has a through via hole. The through substrate via structure is disposed in the through via hole. The through substrate via structure disposed in the through via hole includes a liner structure and a metal layer. The liner structure includes at least two insulation liners and at least one conductive shielding layer disposed between the insulation liners, in which the insulation liners and the at least one conductive shielding layer conformally cover a sidewall and a bottom of the through via hole. The metal layer covers the liner structure and fills the through via hole.

Abstract: A semiconductor device includes a substrate and a through substrate via structure. The substrate has a through via hole. The through substrate via structure is disposed in the through via hole. The through substrate via structure disposed in the through via hole includes a liner structure and a metal layer. The liner structure includes at least two insulation liners and at least one conductive shielding layer disposed between the insulation liners, in which the insulation liners and the at least one conductive shielding layer conformally cover a sidewall and a bottom of the through via hole. The metal layer covers the liner structure and fills the through via hole.

Abstract: A bipolar junction transistor includes an emitter, a base contact, a collector and a shallow trench isolation. The base contact has two base fingers that form a corner to receive the emitter. The collector has two collector fingers extending along the base fingers of the base contact. The shallow trench isolation is disposed in between the emitter and the base contact and in between the base contact and the collector.

Abstract: According to an exemplary embodiment, a semiconductor device is provided. The semiconductor device includes a first seal ring and a first circuit. The first circuit includes a first capacitor and a first inductor connected in series. The first circuit is connected between the first seal ring and a ground.

Abstract: A semiconductor device comprises a guarded circuit. The semiconductor device also comprises a guard ring surrounding the guarded circuit. The semiconductor device further comprises a resonant circuit coupled with the guard ring. The resonant circuit comprises an input node coupled with the guard ring. The resonant circuit also comprises an inductor. The resonant circuit further comprises a capacitor coupled with the inductor. The resonant circuit additionally comprises a ground node configured to carry a ground voltage. The inductor and the capacitor are coupled between the input node and the ground node.

Abstract: A bipolar junction transistor includes an emitter, a base contact, a collector and a shallow trench isolation. The base contact has two base fingers that form a corner to receive the emitter. The collector has two collector fingers extending along the base fingers of the base contact. The shallow trench isolation is disposed in between the emitter and the base contact and in between the base contact and the collector.

Abstract: A bipolar junction transistor includes an emitter, a base contact, a collector and a shallow trench isolation. The base contact has two base fingers that form a corner to receive the emitter. The collector has two collector fingers extending along the base fingers of the base contact. The shallow trench isolation is disposed in between the emitter and the base contact and in between the base contact and the collector.

Abstract: According to an exemplary embodiment, a semiconductor device is provided. The semiconductor device includes a first seal ring and a first circuit. The first circuit includes a first capacitor and a first inductor connected in series. The first circuit is connected between the first seal ring and a ground.

Abstract: A semiconductor device comprises a guarded circuit. The semiconductor device also comprises a guard ring surrounding the guarded circuit. The semiconductor device further comprises a resonant circuit coupled with the guard ring. The resonant circuit comprises an input node coupled with the guard ring. The resonant circuit also comprises an inductor. The resonant circuit further comprises a capacitor coupled with the inductor. The resonant circuit additionally comprises a ground node configured to carry a ground voltage. The inductor and the capacitor are coupled between the input node and the ground node.

Abstract: According to an exemplary embodiment, a semiconductor device is provided. The semiconductor device includes a first seal ring and a first circuit. The first circuit includes a first capacitor and a first inductor connected in series. The first circuit is connected between the first seal ring and a ground.

Abstract: According to an exemplary embodiment, a semiconductor device is provided. The semiconductor device includes a first seal ring and a first circuit. The first circuit includes a first capacitor and a first inductor connected in series. The first circuit is connected between the first seal ring and a ground.

Abstract: An isolation structure in a semiconductor device absorbs electronic noise and prevents substrate leakage currents from reaching other devices and signals. The isolation structure provides a duality of deep N-well (“DNW”) isolation structures surrounding an RF device or other source of electronic noise. The DNW isolation structures extend into the substrate at a depth of at least about 2.5 ?m and may be coupled to VDD. P+ guard rings are also provided in some embodiments and are provided inside, outside or between the dual DNW isolation structures.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes an inductor formed on a substrate and configured to be operable with a current of a frequency; and dummy metal features configured between the inductor and the substrate, the dummy metal features having a first width less than 2 times of a skin depth associated with the frequency.

Abstract: An isolation structure in a semiconductor device absorbs electronic noise and prevents substrate leakage currents from reaching other devices and signals. The isolation structure provides a duality of deep N-well (“DNW”) isolation structures surrounding an RF device or other source of electronic noise. The DNW isolation structures extend into the substrate at a depth of at least about 2.5 ?m and may be coupled to VDD. P+ guard rings are also provided in some embodiments and are provided inside, outside or between the dual DNW isolation structures.