Patents by Inventor Hsiao-Chung LIANG

Hsiao-Chung LIANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240088224
    Abstract: A semiconductor structure includes a first gate structure, a second gate structure coupled to the first gate structure, a source region, a first drain region, and a second drain region. The source region is surrounded by the first gate structure and the second gate structure. The first drain region is separated from the source region by the first gate structure. The second drain region is separated from the source region by the second gat structure. A shape of the first drain region and a shape of the second drain region are different from each other from a plan view.
    Type: Application
    Filed: November 14, 2023
    Publication date: March 14, 2024
    Inventors: HSING-I TSAI, FU-HUAN TSAI, CHIA-CHUNG CHEN, HSIAO-CHUN LEE, CHI-FENG HUANG, CHO-YING LU, VICTOR CHIANG LIANG
  • Patent number: 11749582
    Abstract: A package structure includes a bottom plate, a semiconductor package, a top plate, a screw and an anti-loosening coating. The semiconductor package is disposed over the bottom plate. The top plate is disposed over the semiconductor package, and includes an internal thread in a screw hole of the top plate. The screw penetrates through the bottom plate, the semiconductor package and the top plate, and includes an external thread. The external thread of the screw is engaged to the internal thread of the top plate, and the anti-loosening coating is adhered between the external thread and the internal thread.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: September 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chia Lai, Chen-Hua Yu, Chung-Shi Liu, Hsiao-Chung Liang, Hao-Yi Tsai, Chien-Ling Hwang, Kuo-Lung Pan, Pei-Hsuan Lee, Tin-Hao Kuo, Chih-Hsuan Tai
  • Publication number: 20220359343
    Abstract: A package structure includes a bottom plate, a semiconductor package, a top plate, a screw and an anti-loosening coating. The semiconductor package is disposed over the bottom plate. The top plate is disposed over the semiconductor package, and includes an internal thread in a screw hole of the top plate. The screw penetrates through the bottom plate, the semiconductor package and the top plate, and includes an external thread. The external thread of the screw is engaged to the internal thread of the top plate, and the anti-loosening coating is adhered between the external thread and the internal thread.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 10, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chia Lai, Chen-Hua Yu, Chung-Shi Liu, Hsiao-Chung Liang, Hao-Yi Tsai, Chien-Ling Hwang, Kuo-Lung Pan, Pei-Hsuan Lee, Tin-Hao Kuo, Chih-Hsuan Tai
  • Patent number: 11444002
    Abstract: A package structure includes a bottom plate, a semiconductor package, a top plate, a screw and an anti-loosening coating. The semiconductor package is disposed over the bottom plate. The top plate is disposed over the semiconductor package, and includes an internal thread in a screw hole of the top plate. The screw penetrates through the bottom plate, the semiconductor package and the top plate, and includes an external thread. The external thread of the screw is engaged to the internal thread of the top plate, and the anti-loosening coating is adhered between the external thread and the internal thread.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: September 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chia Lai, Chen-Hua Yu, Chung-Shi Liu, Hsiao-Chung Liang, Hao-Yi Tsai, Chien-Ling Hwang, Kuo-Lung Pan, Pei-Hsuan Lee, Tin-Hao Kuo, Chih-Hsuan Tai
  • Publication number: 20220037228
    Abstract: A package structure includes a bottom plate, a semiconductor package, a top plate, a screw and an anti-loosening coating. The semiconductor package is disposed over the bottom plate. The top plate is disposed over the semiconductor package, and includes an internal thread in a screw hole of the top plate. The screw penetrates through the bottom plate, the semiconductor package and the top plate, and includes an external thread. The external thread of the screw is engaged to the internal thread of the top plate, and the anti-loosening coating is adhered between the external thread and the internal thread.
    Type: Application
    Filed: July 29, 2020
    Publication date: February 3, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Chia Lai, Chen-Hua Yu, Chung-Shi Liu, Hsiao-Chung Liang, Hao-Yi Tsai, Chien-Ling Hwang, Kuo-Lung Pan, Pei-Hsuan Lee, Tin-Hao Kuo, Chih-Hsuan Tai
  • Patent number: 11233032
    Abstract: Embodiments of mechanisms for forming a package are provided. The package includes a substrate and a contact pad formed on the substrate. The package also includes a conductive pillar bonded to the contact pad through solder formed between the conductive pillar and the contact pad. The solder is in direct contact with the conductive pillar.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: January 25, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yeong-Jyh Lin, Hsin-Hung Liao, Chien-Ling Hwang, Bor-Ping Jang, Hsiao-Chung Liang, Chung-Shi Liu
  • Patent number: 10985135
    Abstract: A method includes placing a plurality of dummy dies over a carrier, placing a plurality of device dies over the carrier, molding the plurality of dummy dies and the plurality of device dies in a molding compound, forming redistribution line over and electrically coupled to the device dies, and performing a die-saw to separate the device dies and the molding compound into a plurality of packages.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Bor-Ping Jang, Jen-Chun Liao, Yeong-Jyh Lin, Hsiao-Chung Liang, Chung-Shi Liu
  • Patent number: 10804234
    Abstract: The present disclosure, in some embodiments, relates to a semiconductor structure. The semiconductor structure includes a substrate and a first conductive pad arranged over the substrate. A boundary structure is on an upper surface of the substrate around the first conductive pad. The boundary structure has one or more sidewalls defining an opening with a round shape over the first conductive pad.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien Ling Hwang, Yeong-Jyh Lin, Bor-Ping Jang, Hsiao-Chung Liang
  • Publication number: 20200118969
    Abstract: A method includes placing a plurality of dummy dies over a carrier, placing a plurality of device dies over the carrier, molding the plurality of dummy dies and the plurality of device dies in a molding compound, forming redistribution line over and electrically coupled to the device dies, and performing a die-saw to separate the device dies and the molding compound into a plurality of packages.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Inventors: Chien Ling Hwang, Bor-Ping Jang, Jen-Chun Liao, Yeong-Jyh Lin, Hsiao-Chung Liang, Chung-Shi Liu
  • Publication number: 20200105710
    Abstract: Embodiments of mechanisms for forming a package are provided. The package includes a substrate and a contact pad formed on the substrate. The package also includes a conductive pillar bonded to the contact pad through solder formed between the conductive pillar and the contact pad. The solder is in direct contact with the conductive pillar.
    Type: Application
    Filed: December 4, 2019
    Publication date: April 2, 2020
    Inventors: Yeong-Jyh Lin, Hsin-Hung Liao, Chien-Ling Hwang, Bor-Ping Jang, Hsiao-Chung Liang, Chung-Shi Liu
  • Patent number: 10510712
    Abstract: A method includes placing a plurality of dummy dies over a carrier, placing a plurality of device dies over the carrier, molding the plurality of dummy dies and the plurality of device dies in a molding compound, forming redistribution line over and electrically coupled to the device dies, and performing a die-saw to separate the device dies and the molding compound into a plurality of packages.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Bor-Ping Jang, Hsin-Hung Liao, Yeong-Jyh Lin, Hsiao-Chung Liang, Chung-Shi Liu
  • Patent number: 10504870
    Abstract: Embodiments of mechanisms for forming a package are provided. The package includes a substrate and a contact pad formed on the substrate. The package also includes a conductive pillar bonded to the contact pad through solder formed between the conductive pillar and the contact pad. The solder is in direct contact with the conductive pillar.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yeong-Jyh Lin, Hsin-Hung Liao, Chien Ling Hwang, Bor-Ping Jang, Hsiao-Chung Liang, Chung-Shi Liu
  • Publication number: 20190237422
    Abstract: The present disclosure, in some embodiments, relates to a semiconductor structure. The semiconductor structure includes a substrate and a first conductive pad arranged over the substrate. A boundary structure is on an upper surface of the substrate around the first conductive pad. The boundary structure has one or more sidewalls defining an opening with a round shape over the first conductive pad.
    Type: Application
    Filed: April 12, 2019
    Publication date: August 1, 2019
    Inventors: Chien Ling Hwang, Yeong-Jyh Lin, Bor-Ping Jang, Hsiao-Chung Liang
  • Patent number: 10276531
    Abstract: The present disclosure relates to a semiconductor device. In some embodiments, the semiconductor device has a first plurality of conductive pads arranged over a first substrate. A conductive solder material is arranged over and is electrically connected to the first plurality of conductive pads. A first boundary structure separates each conductive pad of the first plurality of conductive pads from an adjacent conductive pad of the first plurality of conductive pads. A die is arranged over the first substrate. The die has outermost sidewalls that are laterally separated from first and second ones of the first plurality of conductive pads by the first boundary structure.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien Ling Hwang, Yeong-Jyh Lin, Bor-Ping Jang, Hsiao-Chung Liang
  • Publication number: 20190123018
    Abstract: A method includes placing a plurality of dummy dies over a carrier, placing a plurality of device dies over the carrier, molding the plurality of dummy dies and the plurality of device dies in a molding compound, forming redistribution line over and electrically coupled to the device dies, and performing a die-saw to separate the device dies and the molding compound into a plurality of packages.
    Type: Application
    Filed: December 17, 2018
    Publication date: April 25, 2019
    Inventors: Chien Ling Hwang, Bor-Ping Jang, Hsin-Hung Liao, Yeong-Jyh Lin, Hsiao-Chung Liang, Chung-Shi Liu
  • Patent number: 10157881
    Abstract: A method includes placing a plurality of dummy dies over a carrier, placing a plurality of device dies over the carrier, molding the plurality of dummy dies and the plurality of device dies in a molding compound, forming redistribution line over and electrically coupled to the device dies, and performing a die-saw to separate the device dies and the molding compound into a plurality of packages.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Bor-Ping Jang, Hsin-Hung Liao, Yeong-Jyh Lin, Hsiao-Chung Liang, Chung-Shi Liu
  • Publication number: 20180005976
    Abstract: Embodiments of mechanisms for forming a package are provided. The package includes a substrate and a contact pad formed on the substrate. The package also includes a conductive pillar bonded to the contact pad through solder formed between the conductive pillar and the contact pad. The solder is in direct contact with the conductive pillar.
    Type: Application
    Filed: September 18, 2017
    Publication date: January 4, 2018
    Inventors: Yeong-Jyh Lin, Hsin-Hung Liao, Chien Ling Hwang, Bor-Ping Jang, Hsiao-Chung Liang, Chung-Shi Liu
  • Patent number: 9768142
    Abstract: Embodiments of mechanisms for forming a package are provided. The package includes a substrate and a contact pad formed on the substrate. The package also includes a conductive pillar bonded to the contact pad through solder formed between the conductive pillar and the contact pad. The solder is in direct contact with the conductive pillar.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yeong-Jyh Lin, Hsin-Hung Liao, Chien Ling Hwang, Bor-Ping Jang, Hsiao-Chung Liang, Chung-Shi Liu
  • Publication number: 20170256513
    Abstract: The present disclosure relates to a semiconductor device. In some embodiments, the semiconductor device has a first plurality of conductive pads arranged over a first substrate. A conductive solder material is arranged over and is electrically connected to the first plurality of conductive pads. A first boundary structure separates each conductive pad of the first plurality of conductive pads from an adjacent conductive pad of the first plurality of conductive pads. A die is arranged over the first substrate. The die has outermost sidewalls that are laterally separated from first and second ones of the first plurality of conductive pads by the first boundary structure.
    Type: Application
    Filed: May 16, 2017
    Publication date: September 7, 2017
    Inventors: Chien Ling Hwang, Yeong-Jyh Lin, Bor-Ping Jang, Hsiao-Chung Liang
  • Patent number: 9659891
    Abstract: A semiconductor device includes a substrate and a first conductive pad on a top surface of the substrate. The semiconductor device further includes a boundary structure on the top surface of the substrate around the conductive pad.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: May 23, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien Ling Hwang, Yeong-Jyh Lin, Bor-Ping Jang, Hsiao-Chung Liang