Abstract: A high-frequency clock generator with low power consumption is made up of a single phase-locked loop and a serially-connected sampling circuit coupled thereto. The phase-locked loop includes a voltage-controlled oscillator which is configured to provide multiple low-frequency oscillating clock signals each of which has the same frequency but with different phases. The sampling circuit includes at least one stage of sampler, and each stage of sampler includes at least one sampling unit. The sampling circuit samples the low-frequency oscillating clock signals with different phase, in order to generate a clock signal with a frequency being 2n times as the frequency of the low-frequency oscillating clock signals generated by the phase-locked loop, and where n is the number of stages of the sampler in the sampling circuit.