Abstract: The invention provides a method for serial data transmission. First, a chip select signal is enabled to a device for serial data transmission. Data stored in a first buffer of a controller is then transmitted to a second buffer of the device. A clock signal is then halted after data stored in the first buffer is completely transmitted. The first buffer is then refreshed with data newly received by the controller while the clock signal is halted. The clock signal is the restarted to operate the device after the first buffer is refreshed. Refreshed data stored in the first buffer is then transmitted to the second buffer while the clock signal is oscillating.

Abstract: An embodiment of a computer system comprises a south-bridge. The south-bridge comprises a controller including a buffer for communicating with electronic devices. When detecting that a Reset# signal is asserted, the buffer is set to a Hi-Impedance state to separate the controller from the electronic device. The Reset# signal indicates a full system reset.

Abstract: The invention provides a method for serial data transmission. First, a chip select signal is enabled to a device for serial data transmission. Data stored in a first buffer of a controller is then transmitted to a second buffer of the device. A clock signal is then halted after data stored in the first buffer is completely transmitted. The first buffer is then refreshed with data newly received by the controller while the clock signal is halted. The clock signal is the restarted to operate the device after the first buffer is refreshed. Refreshed data stored in the first buffer is then transmitted to the second buffer while the clock signal is oscillating.

Abstract: The invention provides a method for Serial-Peripheral-Interface (SPI) data transmission. First, data stored in a first buffer of an SPI controller is transmitted to a second buffer of an SPI slave. A clock signal according to which the SPI slave operates is halted after data stored in the first buffer is completely transmitted. The first buffer is then refreshed with data newly received by the SPI controller while the clock signal is halted. The clock signal is then restarted to operate the SPI slave after the first buffer is refreshed. Refreshed data stored in the first buffer is then transmitted to the second buffer while the clock signal is oscillating. Halting of the clock signal, refreshing of the first buffer, restarting of the clock signal, and transmitting of refreshed data are repeated until the second buffer is full. The buffer size of the second buffer greatly exceeds that of the first buffer.

Abstract: The invention provides a method for Serial-Peripheral-Interface (SPI) data transmission. First, data stored in a first buffer of an SPI controller is transmitted to a second buffer of an SPI slave. A clock signal according to which the SPI slave operates is halted after data stored in the first buffer is completely transmitted. The first buffer is then refreshed with data newly received by the SPI controller while the clock signal is halted. The clock signal is then restarted to operate the SPI slave after the first buffer is refreshed. Refreshed data stored in the first buffer is then transmitted to the second buffer while the clock signal is oscillating. Halting of the clock signal, refreshing of the first buffer, restarting of the clock signal, and transmitting of refreshed data are repeated until the second buffer is full. The buffer size of the second buffer greatly exceeds that of the first buffer.

Abstract: Device information management systems and methods for use in a computer system are provided. The system comprises an application device, a south bridge chip, a memory and an arbitrator. The application device and the south bridge chip couple to the arbitrator, and couple to the memory via the arbitrator. The arbitrator receives an access request from a specific device among the application devices and the south bridge chip. When data transmission between the arbitrator and the memory is idle, the arbitrator transmits a grant signal to the specific device. After receiving the grant signal, the specific device begins access from the memory.

Abstract: An embodiment of a computer system comprises a south-bridge. The south-bridge comprises a controller including a buffer for communicating with electronic devices. When detecting that a Reset# signal is asserted, the buffer is set to a Hi-Impedance state to separate the controller from the electronic device. The Reset# signal indicates a full system reset.