Abstract: A memory device and a method of making the memory device are provided. A first dielectric layer is formed on a substrate, a floating gate is formed on the first dielectric layer, a second dielectric layer is formed on the floating gate, a control gate is formed on the second dielectric layer, and at least one film, including a conformal film, is formed over a surface of the memory device.

Abstract: A method of manufacturing a non-volatile memory device includes forming a number of memory cells. The method also includes depositing a first dielectric layer over the memory cells, where the first dielectric layer is a conformal layer having a substantially uniform thickness. The method further includes depositing a second dielectric layer over the first dielectric layer. Together, the first and second dielectric layers form an interlayer dielectric without voids.

Abstract: A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.

Abstract: A memory device and a method of making the memory device are provided. A first dielectric layer is formed on a substrate, a floating gate is formed on the first dielectric layer, a second dielectric layer is formed on the floating gate, a control gate is formed on the second dielectric layer, and at least one film, including a conformal film, is formed over a surface of the memory device.

Abstract: A method of manufacturing a non-volatile memory device includes forming a number of memory cells. The method also includes depositing a first dielectric layer over the memory cells, where the first dielectric layer is a conformal layer having a substantially uniform thickness. The method further includes depositing a second dielectric layer over the first dielectric layer. Together, the first and second dielectric layers form an interlayer dielectric without voids.

Abstract: A memory device and a method of making the memory device are provided. A first dielectric layer is formed on a substrate, a floating gate is formed on the first dielectric layer, a second dielectric layer is formed on the floating gate, a control gate is formed on the second dielectric layer, and at least one film, including a conformal film, is formed over a surface of the memory device.

Abstract: A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.

Abstract: A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.

Abstract: A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.

Abstract: A method for testing tunnel oxide on a memory-related structure. In one method embodiment, the present invention accesses a memory-related structure during a manufacturing process. Next, the present embodiment applies a constant voltage to a gate of the memory-related structure. The present embodiment then measures a first gate current for the memory-related structure when the constant voltage is initially applied, to obtain a first value. Next, the present embodiment measures a second gate current for the memory-related structure a period of time after the constant voltage is initially applied to obtain a second value. A calculation of ratio of the second value to the first value is then performed. The present embodiment then generates a graph of the first value and the ratio of the second value to the first value as a function of time, wherein a decrease in the graph signifies stress induced electron trapping behavior of the tunnel oxide.

Abstract: A method of fabricating a semiconductor device. A first layer comprising a first material is deposited to a first thickness on a sidewall of a stacked gate. A second layer comprising a second material is deposited over the first layer. The second layer is deposited without the first layer being etched; hence, the first thickness is unchanged along the sidewall. The second layer is reduced to a second thickness along the sidewall. The first layer and the second layer in combination form a spacer along the sidewall that has a thickness corresponding to the first thickness and the second thickness. Thus, the spacer can be formed using a single etch, reducing the number of processing steps. In addition, the first layer protects shallow trench filler material from gouging during the etch.

Abstract: A method of protecting a stacked gate structure of a flash memory device during fabrication is disclosed. Additionally, the manner of protecting the stacked gate structure during fabrication is simple to implement and is cost-effective. In particular, a protective layer is deposited on the stacked gate structure to protect the stacked gate structure before a resist removal process is performed a second time. Despite undergoing two resist removal processes, the stacked gate structure suffers less damage than the convention fabrication techniques, increasing the yield and reliability of the flash memory device.

Abstract: A method (300) of fabricating a semiconductor device. An oxide layer (220) is produced on a sidewall (211) of a stacked gate (210) and over a shallow trench (212) adjacent to the stacked gate. The thickness of the oxide layer is sufficient to withstand a subsequent etch. A first layer (222) of material is deposited over the oxide layer. In a first etch, the first layer is reduced to a first thickness along the sidewall. Because the oxide layer has a depth sufficient to withstand the first etch, the oxide layer serves as a protective layer for the shallow trench during the first etch. Accordingly, a protective liner layer does not need to be deposited in addition to the oxide layer.

Abstract: For fabricating a first device within a core region and a second device within a periphery region, of a semiconductor substrate, disposable spacers having a first width are formed at sidewalls of a first gate stack of the core region and a second gate stack of the periphery region. Drain and source junctions of the second device are formed in the periphery region to the sides of the disposable spacers of the second gate stack. The disposable spacers are removed and permanent spacers having a second width are formed at the sidewalls of the first and second gate stacks, with the second width being less than the first width. Silicide is formed with an exposed portion of a drain bit line junction within the core region after forming the permanent spacers.

Abstract: One aspect of the invention relates to a method of manufacturing a flash memory device in which Vss lines are salicided prior to forming memory cell stacks. According to the invention, silicide is aligned to the Vss lines by a layer of temporary material, such as a silicon nitride layer, patterned to form dummy gates. A dielectric layer can be deposited and planarized with the dummy gates prior to their removal. The dielectric layer facilitates selective removal of the dummy gates and formation of memory cell stacks that are properly aligned with the Vss lines and drain regions. The dummy gate concept can be used with methods of forming low resistance Vss lines other than saliciding. One advantage of the invention is that the memory cell stacks are not exposed to high temperature processing used in forming low resistance Vss lines.