Patents by Inventor Hsiao-Hsuan Chou

Hsiao-Hsuan Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • WASHING MACHINE WITH A PLURALITY OF TANKS AND WASHING METHOD THEREOF
    Publication number: 20170159226
    Abstract: A washing machine with a plurality of tanks and the washing method thereof are disclosed. In the present invention, the tanks of the washing machine are determined to wash individually or alternately, water and washing medium are also determined to be recycled or not. By using the washing machine of the present invention, water, washing medium and the washing procedures can be reduced.
    Type: Application
    Filed: March 14, 2016
    Publication date: June 8, 2017
    Inventor: Hsiao-Hsuan CHOU
  • Chip design with power rails under transistors
    Patent number: 6818931
    Abstract: A method and an integrated circuit having power rails under transistors. In a preferred embodiment, power rails are formed over a substrate. Devices, such as FET transistors, are formed over the power rails. A preferred device is an inverter. The method comprises forming a first power rail (VSS) over the substrate. Then forming a second power rail (e.g., VDD) over the first power rail. The second power rail is insulated from the first power rail. Next, transistors are formed over the first and the second power rails.
    Type: Grant
    Filed: June 3, 2003
    Date of Patent: November 16, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Louis Liu, Hsiao-Hsuan Chou
  • Chip design with power rails under transistors
    Publication number: 20030207523
    Abstract: A method and an integrated circuit having power rails under transistors. In a preferred embodiment, power rails are formed over a substrate. Devices, such as FET transistors, are formed over the power rails. A preferred device is an inverter. The method comprises forming a first power rail (VSS) over the substrate. Then forming a second power rail (e.g., VDD) over the first power rail. The second power rail is insulated from the first power rail. Next, transistors are formed over the first and the second power rails.
    Type: Application
    Filed: June 3, 2003
    Publication date: November 6, 2003
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Louis Liu, Hsiao-Hsuan Chou
  • Chip design with power rails under transistors
    Patent number: 6583045
    Abstract: A method and an integrated circuit having power rails under transistors. In a preferred embodiment, power rails are formed over a substrate. Devices, such as FET transistors, are formed over the power rails. A preferred device is an inverter. The method comprises forming a first power rail (VSS) over the substrate. Then forming a second power rail (e.g., VDD) over the first power rail. The second power rail is insulated from the first power rail. Next, transistors are formed over the first and the second power rails.
    Type: Grant
    Filed: November 16, 2001
    Date of Patent: June 24, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Louis Liu, Hsiao-Hsuan Chou