Abstract: A three-dimensional (3D) static random access memory (SRAM) cell includes two PU transistors arranged in a first tier, two PD transistors arranged in a second tier positioned above or below the first tier, and two PG transistors arranged in the first or second tier. The transistors can be fin transistors, and each PU and PD transistor can have a first and second number of fins, respectively. The transistors can also be nanosheet-based transistors, and each PU and PD transistor can have a first and a second nanosheet width, respectively.

Abstract: The present disclosure relates to static random access memory (SRAM). In particular, the disclosure provides a stacked SRAM cell, and a method for fabricating the stacked SRAM cell. The stacked SRAM cell comprises two first transistor structures and two second transistor structures, which form a pair of cross-coupled inverters, an comprises one or two pass gate (PG) transistor structures. Further, the stacked SRAM cell comprises a first power rail and/or a second power rail arranged above the transistor structures, wherein the first power rail is connected by respective first vias to the first transistor structures from above, and/or the second power rail is connected by respective second vias to the second transistor structures from above. The SRAM cell also comprises one or two bit lines arranged below the PG transistor structures. Each bit line is connected by a respective third via to one PG transistor structure from below.

Abstract: A method for forming a semiconductor device is disclosed. The method includes: forming a first bottom and top channel structures, and second bottom and top channel structures, and a sacrificial gate extending across the channel structures; forming an opening in the sacrificial gate, over the first top channel structure and forming a cut through the first top channel structure; forming a dielectric plug in the cut and the opening; removing the sacrificial gate and subsequently forming an RMG structure comprising a first gate stack on the first bottom channel structure and a second gate stack on the second bottom and top channel structures; forming pairs of S/D structures on the first bottom channel structure, the second bottom channel structure, and the second top channel structure; forming S/D contacts on the S/D structures; forming a trench for a cross-couple contact; and forming the cross-couple contact in the trench.

Abstract: A method for forming a semiconductor device is provided. The method includes: forming, over a substrate, a stacked transistor structure comprising: a bottom channel structure and a top channel structure, a gate structure extending across the bottom and top channel structures, a first and a second bottom S/D structure on the bottom channel structure, and a first and a second top S/D structure on the top channel structure; forming a first and a second bottom S/D contact on the first and the second bottom S/D structures; forming a contact isolation layer capping the first and second bottom S/D contacts, and covering the capped first and second bottom S/D contacts with an ILD layer; forming a first contact trench; forming a second contact trench; and forming a first top S/D contact.

Abstract: Example embodiments relate to methods for forming a semiconductor device. One example method includes forming a device structure on a substrate, where the device structure includes a device layer stack that includes a bottom device sub-stack that includes at least one bottom channel layer and a top device sub-stack that includes at least one top channel layer, a sacrificial gate structure extending across the device layer stack, and bottom source/drain structures on opposite ends of at least one bottom channel layer. The method also includes forming an opening exposing the top device sub-stack, wherein forming the opening includes etching the sacrificial gate structure, forming a cut through the top device sub-stack by etching back the top device sub-stack from the opening and, subsequent to forming the cut, forming a functional gate stack on the at least one bottom channel layer.

Abstract: A bit cell for a Static Random-Access Memory (SRAM) is provided that includes a first and second pair of complementary transistors as well as a first pass-gate transistor and a second pass-gate transistor. A first inverter gate electrode forms a common gate electrode for the first pair of complementary transistors and a second inverter gate electrode forms a common gate electrode for the second pair of complementary transistors. Further, a first pass gate electrode forms a gate of the first pass-gate transistor and a second pass gate electrode forms a gate of the second pass-gate transistor. A first and a second dielectric wall are also provided, separating the first pass gate electrode from the first inverter gate electrode, and the second pass gate electrode from the second inverter gate electrode.

Abstract: A bit cell for a Static Random-Access Memory (SRAM) is provided that includes first and second sets of transistors. Each set of transistors includes a respective pass-gate transistor and a respectively stacked complementary transistor pair of an upper transistor and a lower transistor. A source/drain terminal of a lower transistor of each set of transistors is connected to a respective first power supply extending in a first power supply track arranged below the lower transistor, whereas a source/drain terminal of an upper transistor of each set of transistors is connected to a respective second power supply extending in a second power supply track arranged above the upper transistor.