Abstract: A cell trace circuit includes a memory cell, a voltage generator and a measuring circuit. The memory cell has a resistor and a memory layer coupled in series to have a top electrode, a middle electrode and a bottom electrode, wherein the resistor and the memory layer are coupled at the middle electrode. The voltage generator provides a test bias to the memory cell ranging from a negative voltage to a positive voltage in a reset path or ranging from the positive voltage to the negative voltage in a set path. The measuring circuit is to determine a current (I) and a voltage (V) crossing the memory layer by the test bias.

Abstract: A non-volatile memory includes a plurality of data storage units arranged in an array, a plurality of redundant data storage units arranged in at least one row and a plurality of redundant address storage units arranged in at least one row. A storage size of each of the data storage units is word. Each of the data storage units is addressable by a row address and a column address. One of the redundant data storage units in a first column is configured to substitute for one of the data storage units in a second column. One of the redundant address storage units in a third column is configured to record the row address representative of the substituted one of the data storage units.

Abstract: A non-volatile memory includes a plurality of data storage units arranged in an array, a plurality of redundant data storage units arranged in at least one row and a plurality of redundant address storage units arranged in at least one row. A storage size of each of the data storage units is word. Each of the data storage units is addressable by a row address and a column address. One of the redundant data storage units in a first column is configured to substitute for one of the data storage units in a second column. One of the redundant address storage units in a third column is configured to record the row address representative of the substituted one of the data storage units.

Abstract: A non-volatile memory cell includes a tunneling part; a coupling device; a read transistor; a first select transistor connected to the read transistor forming a read path with the read transistor in a read mode; an erase tunneling structure forming a tunneling ejection path in an erase mode; and a program tunneling structure forming a tunneling injection path in an program mode; wherein the read path is different from the tunneling ejection path and the tunneling injection path.

Abstract: A non-volatile memory cell comprises a tunneling part; a coupling device; a read transistor; a first select transistor connected to the read transistor forming a read path with the read transistor in a read mode; an erase tunneling structure forming a tunneling ejection path in an erase mode; and a program tunneling structure forming a tunneling injection path in an program mode; wherein the read path is different from the tunneling ejection path and the tunneling injection path.

Abstract: A memory erasing method and a driving circuit thereof are introduced, when cells are selected to be erased, the method includes setting gates of cells which are not selected to be erased and are located at a selected block, drains of all the cells in a selected bank, and the gate of the unselected cells to be floating; supplying a positive voltage to all the sources in a selected bank and their shared P well and N well; and supplying a negative voltage to the gates of the cells located in a selected block and selected to be erased. Accordingly, a positive coupling voltage from P wells is received whenever gates are floating, so as to inhibit erasure of unselected blocks and thereby streamline decoding, thus making it easy to attain further expansion of blocks or banks with a small layout area and partition of sectors in the blocks.

Abstract: A power reset circuit with zero standby current consumption includes a power storage unit, first, second, and third voltage detection units, a switching unit, and a power reset unit. The power storage unit stores electric power by a supply voltage source. The first, second, and third voltage detection units are connected to the supply voltage source to start a switching circuit of the first, second, and third voltage detection units in accordance with a change in a normal supply stage, a shutdown stage, and a voltage ramp-up stage of the supply voltage source, control a voltage level of the power reset unit, and thereby generate the power reset signal. Accordingly, the power reset circuit does not consume current in a standby state (the normal supply stage of the supply voltage source) and thus is characterized by zero current consumption.

Abstract: A memory erasing method and a driving circuit thereof are introduced, when cells are selected to be erased, the method includes setting gates of cells which are not selected to be erased and are located at a selected block, drains of all the cells in a selected bank, and the gate of the unselected cells to be floating; supplying a positive voltage to all the sources in a selected bank and their shared P well and N well; and supplying a negative voltage to the gates of the cells located in a selected block and selected to be erased. Accordingly, a positive coupling voltage from P wells is received whenever gates are floating, so as to inhibit erasure of unselected blocks and thereby streamline decoding, thus making it easy to attain further expansion of blocks or banks with a small layout area and partition of sectors in the blocks.

Abstract: A wordline internal current leakage self-detection method, system and a computer-readable storage medium thereof employ the originally existed high voltage supply unit and the voltage detector connected to the wordline in the flash memory device, in which the high voltage supply unit applies the test signal to the selected wordline, and the voltage detector detects the voltage signal of the wordline. By comparing the test signal with the voltage signal, the wordline will be indicated as current leakage when the voltage signal is lower than the test signal.

Abstract: In a flash memory device with switching I/O structure for applying in flash memory products, depending on actual need for input and/or output pins, other pins may be flexibly switched to input, output, or bi-directional pins through software and/or hardware and/or CAM access. Therefore, data input and/or output rate may be changed through switching the I/O structure. Moreover, after the I/O configuration, the switched other pins may start data input/output immediately after the flash memory is started to operate, without the need of waiting for several input/output phases.

Abstract: A single-poly non-volatile memory includes a storing node, a control node and a floating gate. While a programming operation is executed, a bit line is provided with a low voltage and a control line is provided with a high voltage so that a coupling voltage occurs in the floating gate. The voltage difference between the floating gate and the storing node is able to send electrons into the floating gate, but the voltage difference between the floating gate and the control node is not enough to expel electrons from the floating gate. While an erasing operation is executed, a bit line is provided with a high voltage and a control line is provided with a low voltage so that a coupling voltage occurs on the floating gate. The voltage difference between the floating gate and the storing node is able to expel electrons from the floating gate, but the voltage difference between the floating gate and the control node is not enough to send electrons into the floating gate.

Abstract: A single-poly non-volatile memory includes a storing node, a control node and a floating gate. While a programming operation is executed, a bit line is provided with a low voltage and a control line is provided with a high voltage so that a coupling voltage occurs in the floating gate. The voltage difference between the floating gate and the storing node is able to send electrons into the floating gate, but the voltage difference between the floating gate and the control node is not enough to expel electrons from the floating gate. While an erasing operation is executed, a bit line is provided with a high voltage and a control line is provided with a low voltage so that a coupling voltage occurs on the floating gate. The voltage difference between the floating gate and the storing node is able to expel electrons from the floating gate, but the voltage difference between the floating gate and the control node is not enough to send electrons into the floating gate.

Abstract: A method and system is disclosed for a wordline driver circuit used for a memory device. It has a logic stage operating between a ground voltage and a first supply voltage and generating a logic stage output signal swinging between the ground voltage and the first supply voltage. It also has a mid voltage stage, operating between a raised ground voltage and a second supply voltage during the programming process, and generating a mid voltage stage output that swings between the second supply voltage and the raised ground voltage. It then has a high voltage stage, operating between the raised ground voltage and a third supply voltage, and generating a wordline driver output swinging between the third supply voltage and the raised ground voltage based on the received mid voltage stage output.

Abstract: A method and system is disclosed for a wordline driver circuit used for a memory device. It has a logic stage operating between a ground voltage and a first supply voltage and generating a logic stage output signal swinging between the ground voltage and the first supply voltage. It also has a mid voltage stage, operating between a raised ground voltage and a second supply voltage during the programming process, and generating a mid voltage stage output that swings between the second supply voltage and the raised ground voltage. It then has a high voltage stage, operating between the raised ground voltage and a third supply voltage, and generating a wordline driver output swinging between the third supply voltage and the raised ground voltage based on the received mid voltage stage output.