Patents by Inventor Hsiao-Hui Chen
Hsiao-Hui Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11948949Abstract: In some embodiments, the present disclosure relates to a device having a semiconductor substrate including a frontside and a backside. On the frontside of the semiconductor substrate are a first source/drain region and a second source/drain region. A gate electrode is arranged on the frontside of the semiconductor substrate and includes a horizontal portion, a first vertical portion, and a second vertical portion. The horizontal portion is arranged over the frontside of the semiconductor substrate and between the first and second source/drain regions. The first vertical portion extends from the frontside towards the backside of the semiconductor substrate and contacts the horizontal portion of the gate electrode structure. The second vertical portion extends from the frontside towards the backside of the semiconductor substrate, contacts the horizontal portion of the gate electrode structure, and is separated from the first vertical portion by a channel region of the substrate.Type: GrantFiled: July 15, 2022Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Yuan Chen, Ching-Chun Wang, Hsiao-Hui Tseng, Jen-Cheng Liu, Jhy-Jyi Sze, Shyh-Fann Ting, Wei Chuang Wu, Yen-Ting Chiang, Chia Ching Liao, Yen-Yu Chen
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Patent number: 11916100Abstract: The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.Type: GrantFiled: March 21, 2022Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsuan-Han Tseng, Chun-Yuan Chen, Lu-Sheng Chou, Hsiao-Hui Tseng, Ching-Chun Wang
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Patent number: 9659920Abstract: The present disclosure relates to an arrangement and a method of performance-aware buffer zone placement for a high-density array of unit cells. A first feature density of the array is measured and maximum variation for a parameter within a unit cell is determined. A look-up table of silicon data is consulted to predict a buffer zone width and gradient value that achieves a variation that is less than the maximum variation for the unit cell. The look-up table contains a suite of silicon test cases of various array and buffer zone geometries, wherein variation of the parameter within a respective test structure is measured and cataloged for the various buffer zone geometries, and is also extrapolated from the suite of silicon test cases. A buffer zone is placed at the border of the array with a width that is less than or equal to the buffer zone width.Type: GrantFiled: March 4, 2015Date of Patent: May 23, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mu-Jen Huang, Hsiao-Hui Chen, Cheok-Kei Lei, Po-Tsun Chen, Yu-Sian Jiang
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Publication number: 20150179627Abstract: The present disclosure relates to an arrangement and a method of performance-aware buffer zone placement for a high-density array of unit cells. A first feature density of the array is measured and maximum variation for a parameter within a unit cell is determined. A look-up table of silicon data is consulted to predict a buffer zone width and gradient value that achieves a variation that is less than the maximum variation for the unit cell. The look-up table contains a suite of silicon test cases of various array and buffer zone geometries, wherein variation of the parameter within a respective test structure is measured and cataloged for the various buffer zone geometries, and is also extrapolated from the suite of silicon test cases. A buffer zone is placed at the border of the array with a width that is less than or equal to the buffer zone width.Type: ApplicationFiled: March 4, 2015Publication date: June 25, 2015Inventors: Mu-Jen Huang, Hsiao-Hui Chen, Cheok-Kei Lei, Po-Tsun Chen, Yu-Sian Jiang
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Patent number: 8978000Abstract: The present disclosure relates to an arrangement and a method of performance-aware buffer zone placement for a high-density array of unit cells. A first feature density of the array is measured and maximum variation for a parameter within a unit cell is determined. A look-up table of silicon data is consulted to predict a buffer zone width and gradient value that achieves a variation that is less than the maximum variation for the unit cell. The look-up table contains a suite of silicon test cases of various array and buffer zone geometries, wherein variation of the parameter within a respective test structure is measured and cataloged for the various buffer zone geometries, and is also extrapolated from the suite of silicon test cases. A buffer zone is placed at the border of the array with a width that is less than or equal to the buffer zone width.Type: GrantFiled: December 27, 2012Date of Patent: March 10, 2015Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.Inventors: Mu-Jen Huang, Hsiao-Hui Chen, Cheok-Kei Lei, Po-Tsun Chen, Yu-Sian Jiang
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Patent number: 8875076Abstract: A method and layout generating machine for generating a layout for a device having FinFETs from a first layout for a device having planar transistors are disclosed. A planar layout with a plurality of FinFET active areas is received and corresponding FinFET active areas are generated with active area widths. Mandrels are generated according to the active area widths and adjusted such that a beta ratio of a beta number for each FinFET active area to a beta number for each corresponding planar active area is within a predetermined beta ratio range.Type: GrantFiled: March 28, 2014Date of Patent: October 28, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Tang Lin, Cheok-Kei Lei, Shu-Yu Chen, Yu-Ning Chang, Hsiao-Hui Chen, Chih-Sheng Chang, Chien-Wen Chen, Clement Hsingjen Wann
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Publication number: 20140215420Abstract: A method and layout generating machine for generating a layout for a device having FinFETs from a first layout for a device having planar transistors are disclosed. A planar layout with a plurality of FinFET active areas is received and corresponding FinFET active areas are generated with active area widths. Mandrels are generated according to the active area widths and adjusted such that a beta ratio of a beta number for each FinFET active area to a beta number for each corresponding planar active area is within a predetermined beta ratio range.Type: ApplicationFiled: March 28, 2014Publication date: July 31, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Tang LIN, Cheok-Kei LEI, Shu-Yu CHEN, Yu-Ning CHANG, Hsiao-Hui CHEN, Chih-Sheng CHANG, Chien-Wen CHEN, Clement Hsingjen WANN
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Patent number: 8789004Abstract: A method and system optimizes or improves an electronic design by analyzing various signal paths in the electronic design and selecting certain critical paths, for example, failed-timing paths, to optimize. The optimizing method extracts the cascaded logic gates to create a megacell representing the function of the critical path, compare test parameters of the megacell with the critical path, and incorporate the megacell into the electronic design if the test parameters improve by an optimizing constraint.Type: GrantFiled: December 15, 2011Date of Patent: July 22, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiao-Hui Chen, Shiue Tsong Shen, Cheok-Kei Lei
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Publication number: 20140189625Abstract: The present disclosure relates to an arrangement and a method of performance-aware buffer zone placement for a high-density array of unit cells. A first feature density of the array is measured and maximum variation for a parameter within a unit cell is determined. A look-up table of silicon data is consulted to predict a buffer zone width and gradient value that achieves a variation that is less than the maximum variation for the unit cell. The look-up table contains a suite of silicon test cases of various array and buffer zone geometries, wherein variation of the parameter within a respective test structure is measured and cataloged for the various buffer zone geometries, and is also extrapolated from the suite of silicon test cases. A buffer zone is placed at the border of the array with a width that is less than or equal to the buffer zone width.Type: ApplicationFiled: December 27, 2012Publication date: July 3, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mu-Jen Huang, Hsiao-Hui Chen, Cheok-Kei Lei, Po-Tsun Chen, Yu-Sian Jiang
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Patent number: 8726220Abstract: A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.Type: GrantFiled: March 9, 2012Date of Patent: May 13, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Tang Lin, Cheok-Kei Lei, Shu-Yu Chen, Yu-Ning Chang, Hsiao-Hui Chen, Chih-Sheng Chang, Chien-Wen Chen, Clement Hsingjen Wann
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Patent number: 8621406Abstract: A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated.Type: GrantFiled: March 9, 2012Date of Patent: December 31, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheok-Kei Lei, Yi-Tang Lin, Hsiao-Hui Chen, Yu-Ning Chang, Shu-Yu Chen, Chien-Wen Chen, Chih-Sheng Chang, Clement Hsingjen Wann
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Publication number: 20130313668Abstract: A photronic device includes a substrate having an opening through the substrate. The photronic device further includes an insulating layer over the substrate including over the opening. The photronic device further includes an active layer over the insulating layer. The photronic device further includes a photoactive device formed in the active layer, wherein the photoactive device is over the opening. The photronic device further includes active electronic circuitry formed in the active layer. The photronic device further includes a reflective layer on the insulating layer in the opening.Type: ApplicationFiled: May 24, 2012Publication date: November 28, 2013Inventors: Gregory S. Spencer, John R. Alvis, Hsiao-Hui Chen, Joseph F. Orcutt, Srivatsa G. Kundalgurki
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Publication number: 20130091483Abstract: A method and system optimizes or improves an electronic design by analyzing various signal paths in the electronic design and selecting certain critical paths, for example, failed-timing paths, to optimize. The optimizing method extracts the cascaded logic gates to create a megacell representing the function of the critical path, compare test parameters of the megacell with the critical path, and incorporate the megacell into the electronic design if the test parameters improve by an optimizing constraint.Type: ApplicationFiled: December 15, 2011Publication date: April 11, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsiao-Hui CHEN, Shiue Tsong SHEN, Cheok-Kei LEI
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Publication number: 20130019219Abstract: System and method for hierarchy reconstruction from a flattened layout are described. In one embodiment, a method for producing a reconstructed layout for an integrated circuit design from an original layout and a revised layout includes, for each pattern of the original layout, determining a pattern of the revised layout that corresponds to the pattern of the original layout; and assigning the corresponding pattern of the revised layout to a temporary instance, the temporary instance corresponding to an instance of the pattern of the original layout and citing to a temporary cell. The method further includes creating a temporary reconstructed layout from the temporary instances; and producing the reconstructed layout from the temporary reconstructed layout, wherein a hierarchy of the reconstructed layout is similar to a hierarchy of the original layout.Type: ApplicationFiled: July 13, 2011Publication date: January 17, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Yu Chen, Yi-Tang Lin, Cheok-Kei Lei, Hsiao-Hui Chen, Yu-Ning Chang, Hsingjen Wann, Chih-Sheng Chang, Chien-Wen Chen
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Publication number: 20120278776Abstract: A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated.Type: ApplicationFiled: March 9, 2012Publication date: November 1, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheok-Kei LEI, Yi-Tang LIN, Hsiao-Hui CHEN, Yu-Ning CHANG, Shu-Yu CHEN, Chien-Wen CHEN, Chih-Sheng CHANG, Clement Hsingjen WANN
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Publication number: 20120278777Abstract: A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.Type: ApplicationFiled: March 9, 2012Publication date: November 1, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Tang LIN, Cheok-Kei LEI, Shu-Yu CHEN, Yu-Ning CHANG, Hsiao-Hui CHEN, Chih-Sheng CHANG, Chien-Wen CHEN, Clement Hsingjen WANN
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Patent number: 8116119Abstract: A static random access memory (SRAM) can include a plurality of columns forming a memory array, wherein each column comprises a plurality of memory cells coupled to bitlines and wordlines, and a write replica circuit generating a signal when data has been written to the write replica circuit. A wordline of the memory array is turned off responsive to the signal. The write replica circuit can include an additional column comprising at least one dual port dummy memory cell, and write detection circuitry coupled to the dual port dummy memory cell detecting when data has been written to the dual port dummy memory cell and responsively generating the signal. The signal generated by the write detection circuitry indicates a successful write operation to the dual port dummy memory cell.Type: GrantFiled: April 12, 2010Date of Patent: February 14, 2012Assignee: Xilinx, Inc.Inventors: Tao Peng, Hsiao Hui Chen
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Patent number: 7746717Abstract: A static random access memory (SRAM) can include an array of memory cells, wherein each memory cell is coupled to one of a plurality of sense amplifiers through a bitline. The SRAM also can include replica bitline circuitry including a replica bitline coupled to a replica bitline amplifier. The replica bitline amplifier can provide a strobe signal to the plurality of sense amplifiers, wherein the replica bitline amplifier includes a feedback path. An SRAM also may include a write replica circuit generating a signal when data has been written to the write replica circuit. A wordline of the memory array can be turned off responsive to the signal.Type: GrantFiled: September 7, 2007Date of Patent: June 29, 2010Assignee: Xilinx, Inc.Inventors: Tao Peng, Hsiao Hui Chen
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Patent number: 7464140Abstract: A method for dynamically determining web resource to be loaded and saving space is provided which determines whether to download a network resource according to a current network bandwidth and available memory space. When a user uses an embedded device in a wireless network environment to download a web-page, the browser only downloads a small part of the network resource to present, and if the user desires to download all network resources, he or she can select to download all network resources, so as to save the download time.Type: GrantFiled: May 10, 2004Date of Patent: December 9, 2008Assignee: Institute For Information IndustryInventors: Yau-Wen Nian, Hsiao-Hui Chen
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Patent number: 7309628Abstract: A semiconductor device is formed as part of an integrated circuit. The semiconductor device, which is formed in an active semiconductor layer, is surrounded by a guardian that provides a diffusion barrier against contaminants and also provides assistance in avoiding dishing above the semiconductor device during chemical mechanical polishing. The dielectric that is above the semiconductor device and inside the guardian is etched to form an opening that receives one of an optical fiber, an electromagnetic signal source, or an electromagnetic signal load. The remaining dielectric is in layers that are of substantially uniform thickness. The guardian is built up in layers that are part of a normal integrated circuit process. These include contact layers, via layers, and interconnect layers.Type: GrantFiled: November 15, 2004Date of Patent: December 18, 2007Inventors: Omar Zia, Hsiao-Hui Chen, Lawrence Cary Gunn, III