Abstract: Semiconductor devices and methods of forming the same are provided. A method of the present disclosure includes depositing an aluminum nitride layer over a substrate, treating the aluminum nitride layer to convert a top portion of the aluminum nitride layer to an aluminum oxynitride layer, depositing a III-V semiconductor layer on the aluminum oxynitride layer, and forming a gate structure over the III-V semiconductor layer.

Abstract: Semiconductor structures and methods of forming the same are provided. An exemplary method incudes forming a first dielectric layer over a first conductive feature, forming a conductive via extending through the first dielectric layer and coupled to the first conductive feature, forming a hard mask layer over the conductive via, patterning the hard mask layer to form a first opening exposing the first dielectric layer; forming a sacrificial layer to partially fill the first opening, forming a porous dielectric layer on the sacrificial layer, after the forming of the porous dielectric layer, selectively removing the sacrificial layer to form an air gap, forming a second dielectric layer over the porous dielectric layer, and replacing a portion of the patterned hard mask layer disposed directly over the conductive via with a second conductive feature.

Abstract: The semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a first dielectric layer, a first metal layer, a second metal layer, a first etching stop layer, a second etching stop layer, a second dielectric layer, a first via and a second via. The first metal layer and the second metal are embedded in the first dielectric layer. The first etching stop layer is disposed on the first dielectric layer. The second etching stop layer is disposed on the first etching stop layer. The second dielectric layer is disposed on the second etching stop layer. The first via and the second via are embedded in the second dielectric layer. A width of the second etching stop layer is smaller a width of the first etching stop layer.

Abstract: An interconnection structure and a manufacturing method thereof are provided. The interconnection structure includes a first dielectric layer, a first conductive feature, a second dielectric layer, and a barrier layer. The first conductive feature is disposed on the first dielectric layer, the second dielectric layer is disposed on the first dielectric layer and surrounds the sidewalls of the first conductive feature, the barrier layer is disposed between the first dielectric layer and the second dielectric layer and between the sidewalls of the first conductive feature and the second dielectric layer.

Abstract: An interconnection structure includes a first dielectric layer, a first conductive feature, a first liner layer, a second conductive feature, a second liner layer, and an air gap. The first conductive feature is disposed in the first dielectric layer. The first liner layer is disposed between the first conductive feature and the first dielectric layer. The second conductive feature penetrates the first dielectric layer. The second liner layer is disposed between the second conductive feature and the first dielectric layer. The air gap is disposed in the first dielectric layer between the first liner layer and the second liner layer. The first liner layer and the second liner layer include metal oxide, metal nitride, or silicon oxide doped carbide.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first low dielectric constant (low-k) layer, a first metal layer, a metal cap layer, a dielectric on dielectric (DoD) layer, an etch stop layer (ESL), a second low-k layer, a metal via and a second metal layer. The dielectric constant of the first low-k layer is less than 4. The first metal layer is embodied in the first low-k layer. The first low-k layer exposes the first metal layer. The metal cap layer is disposed on the first metal layer. The DoD layer is disposed on the first low-k layer. The etch stop layer is disposed on the metal cap layer and the DoD layer. The second low-k layer is disposed above the etch stop layer. The metal via is embodied in the second low-k layer and connected to the first metal layer.

Abstract: A method includes forming a metal layer over a dielectric layer; forming hard masks over the metal layer; etching the metal layer using the hard masks as etch mask to form metal features; selectively forming dielectric liners on opposite sidewalls of each of the metal features, while leaving surfaces of the hard masks and the dielectric layer exposed by the dielectric liners; and forming an inter-metal dielectric layer laterally surrounding the metal features.

Abstract: A semiconductor device package, along with methods of forming such, are described. The semiconductor device package includes a first semiconductor device structure having a first substrate, two first devices disposed on the first substrate, a first interconnection structure disposed over the first substrate and the two first devices, and a first thermal feature disposed through the first substrate and the first interconnection structure. The semiconductor device package further includes a second semiconductor device structure disposed over the first semiconductor device structure having a second interconnection structure disposed over the first interconnection structure, a second substrate disposed over the second interconnection structure, two second devices disposed between the second substrate and the second interconnection structure, and a second thermal feature disposed through the second substrate and the second interconnection structure.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes an electrical interconnect structure, a thermal interconnect structure, and a thermal passivation layer over a substrate. The electrical interconnect structure includes interconnect vias and interconnect wires embedded within interconnect dielectric layers. The thermal interconnect structure is arranged beside the electrical interconnect structure and includes thermal vias, thermal wires, and/or thermal layers. Further, the thermal interconnect structure is embedded within the interconnect dielectric layers. The thermal passivation layer is arranged over a topmost one of the interconnect dielectric layers. The thermal interconnect structure has a higher thermal conductivity than the interconnect dielectric layers.

Abstract: A semiconductor structure includes a base structure including a substrate and a device unit disposed on a front surface of the substrate, a front dielectric portion disposed on the front surface to cover the device unit, a front conductive layer disposed in the front dielectric portion and connected to the device unit, a back dielectric unit disposed on a back surface of the substrate opposite to the front surface and including at least one first part which includes a first dielectric portion having a thermal conductivity which is greater than that of the front dielectric portion, and a back conductive unit which is disposed in the back dielectric unit and connected to the device unit, and which includes at least one first conductive layer disposed in the at least one first part.

Abstract: A method for forming a semiconductor device structure is disclosed. The method includes forming one or more first conductive features in a first dielectric layer, forming a metal layer on each of the one or more first conductive features, forming a first etch stop layer over the metal layer, forming a second etch stop layer on the first etch stop layer, wherein the second etch stop layer is a nitrogen-free layer. The method also includes forming a second dielectric layer on the second etch stop layer, and forming a second conductive feature in the second dielectric layer through the second etch stop layer, the first etch stop layer, and the metal layer.

Abstract: A method of forming a semiconductor structure is provided. A first dielectric layer is formed over a substrate. A first metal pattern is formed through the first dielectric layer. A metal cap is formed over the first metal pattern. A surface portion of the metal cap is silicided to form a metal silicide pattern. A composite etch stop layer is formed on the first dielectric layer and the metal silicide pattern. A second dielectric layer is formed on the composite etch stop structure. A second metal pattern is formed through the second dielectric layer and the composite etch stop structure and landed on the metal silicide pattern.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes an electrical interconnect structure, a thermal interconnect structure, and a thermal passivation layer over a substrate. The electrical interconnect structure includes interconnect vias and interconnect wires embedded within interconnect dielectric layers. The thermal interconnect structure is arranged beside the electrical interconnect structure and includes thermal vias, thermal wires, and/or thermal layers. Further, the thermal interconnect structure is embedded within the interconnect dielectric layers. The thermal passivation layer is arranged over a topmost one of the interconnect dielectric layers. The thermal interconnect structure has a higher thermal conductivity than the interconnect dielectric layers.

Abstract: An interconnection structure includes a first dielectric layer, a first conductive feature disposed in the first dielectric layer, a second dielectric layer on the first dielectric layer, a conductive layer disposed in the second dielectric layer, and a liner layer disposed between the conductive layer and the second dielectric layer, wherein the liner layer has a portion extended over to a top surface of the second dielectric layer. The structure also includes a third dielectric layer on the second dielectric layer, a second conductive feature disposed in the third dielectric layer, wherein the second conductive feature has a portion in direct contact with the conductive layer. The structure further includes a first capping layer disposed between the second conductive feature and the third dielectric layer, and a portion of the first capping layer is extended to cover a top surface of the second conductive feature.

Abstract: An interconnection structure includes a first dielectric layer, a first conductive feature, a second dielectric layer, a conductive layer, a liner layer, a third dielectric layer, a second conductive feature, and a first capping layer. The first conductive feature is disposed in the first dielectric layer. The second dielectric layer is formed on the first dielectric layer, and the second dielectric layer is in direct contact with the first dielectric layer. The conductive layer is disposed in the second dielectric layer. The liner layer is disposed between the conductive layer and the second dielectric layer. The third dielectric layer is formed on the second dielectric layer. The second conductive feature is disposed in the third dielectric layer. The first capping layer is disposed between the second conductive feature and the third dielectric layer.

Abstract: A self-aligned interconnection structure includes a dielectric layer, a conductive feature, a capping layer, a first barrier layer and a second barrier layer. The conductive feature is formed in the dielectric layer, and the conductive feature has a top surface. The capping layer is disposed on the top surface of the conductive feature, and the capping layer does not cover the dielectric layer. The first barrier layer is disposed on the capping layer, and the first barrier layer does not cover the dielectric layer. The second barrier layer covers the first barrier layer and the dielectric layer, and the first barrier layer and the second barrier layer are formed of different materials.

Abstract: An interconnection structure includes a first dielectric layer, a first conductive layer disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer, a second conductive layer disposed in the second dielectric layer in electrical contact with the first conductive layer, a third dielectric layer formed over the second dielectric layer, wherein the third dielectric layer comprises silicon carbon-nitride (SiCN) based material, and a resistor device disposed in the third dielectric layer.

Abstract: A method for forming an interconnect structure is described. In some embodiments, the method includes forming a conductive layer, removing portions of the conductive layer to form a via portion extending upward from a bottom portion, forming a sacrificial layer over the via portion and the bottom portion, recessing the sacrificial layer to a level substantially the same or below a level of a top surface of the bottom portion, forming a first dielectric material over the via portion, the bottom portion, and the sacrificial layer, and removing the sacrificial layer to form an air gap adjacent the bottom portion.

Abstract: A method for making a semiconductor structure, including: forming a conductive layer; forming a patterned mask layer on the conductive layer; patterning the conductive layer to form a recess and a conductive feature; forming a first dielectric layer over the patterned mask layer and filling the recess with the first dielectric layer; patterning the first dielectric layer to form an opening; selectively forming a blocking layer in the opening; forming an etch stop layer to cover the first dielectric layer and exposing the blocking layer; forming on the etch stop layer a second dielectric layer; forming a second dielectric layer on the etch stop layer; patterning the second dielectric layer to form a through hole and exposing the conductive feature; and filling the through hole with an electrically conductive material to form an interconnect electrically connected to the conductive feature.

Abstract: A method for manufacturing a semiconductor device includes preparing an electrically conductive structure including a plurality of electrically conductive features, conformally forming a thermally conductive dielectric capping layer on the electrically conductive structure, conformally forming a dielectric coating layer on the thermally conductive dielectric capping layer, filling a sacrificial material into recesses among the electrically conductive features, recessing the sacrificial material to form sacrificial features in the recesses, forming a sustaining layer over the dielectric coating layer to cover the sacrificial features, and removing the sacrificial features to form air gaps covered by the sustaining layer. The thermally conductive dielectric capping layer has a thermal conductivity higher than that of the dielectric coating layer.