Patents by Inventor Hsiao-Lan Yeh

Hsiao-Lan Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230369151
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first transparent substrate, a conductive layer, an insulating protective layer, a second transparent substrate, a device substrate, and a bonding layer. The first transparent substrate has a first surface and an opposite second surface. The conductive layer is disposed on the second surface of the first transparent substrate. The insulating protective layer covers the conductive layer and the first transparent substrate. The second transparent substrate is disposed above the first transparent substrate, and has a first surface facing the first transparent substrate and an opposite second surface. The device substrate is disposed on the second surface of the second transparent substrate. The bonding layer is bonded to the insulating protective layer and the first surface of the second transparent substrate.
    Type: Application
    Filed: May 1, 2023
    Publication date: November 16, 2023
    Inventors: Hsiao-Lan YEH, Chin-Kang CHEN, Kung-Hua CHENG, Szu-Hui MA LEE, Chi-Jia TONG
  • Patent number: 10388541
    Abstract: A wafer coating system includes a wafer chuck, a flowing insulating material sprayer and a wafer tilting lifting pin. The wafer chuck has a carrier part and a rotating part, which the carrier part is mounted on the rotating part to carry a wafer, and the rotating part is configured to rotate with a predetermined axis. The flowing insulating material sprayer is above the wafer chuck and configured to spray a flowing insulating material to the wafer, and the wafer tilting lifting pin is configured to form a first acute angle between the wafer and direction of gravity.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: August 20, 2019
    Assignee: XINTEC INC.
    Inventors: Yu-Tung Chen, Quan-Qun Su, Chuan-Jin Shiu, Chien-Hui Chen, Hsiao-Lan Yeh, Yen-Shih Ho
  • Patent number: 9947716
    Abstract: A chip package includes a chip, an adhesive layer, and a dam element. The chip has a sensing area, a first surface, and a second surface that is opposite to the first surface. The sensing area is located on the first surface. The adhesive layer covers the first surface of the chip. The dam element is located on the adhesive layer and surrounds the sensing area. The thickness of the dam element is in a range from 20 ?m to 750 ?m, and the wall surface of the dam element surrounding the sensing area is a rough surface.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: April 17, 2018
    Assignee: XINTEC INC.
    Inventors: Yen-Shih Ho, Hsiao-Lan Yeh, Chia-Sheng Lin, Yi-Ming Chang, Po-Han Lee, Hui-Hsien Wu, Jyun-Liang Wu, Shu-Ming Chang, Yu-Lung Huang, Chien-Min Lin
  • Patent number: 9875912
    Abstract: A chip package includes a chip, a first adhesive layer, a second adhesive layer, and a protection cap. The chip has a sensing area, a first surface, a second surface that is opposite to the first surface, and a side surface adjacent to the first and second surfaces. The sensing area is located on the first surface. The first adhesive layer covers the first surface of the chip. The second adhesive layer is located on the first adhesive layer, such that the first adhesive layer is between the first surface and the second adhesive layer. The protection cap has a bottom board and a sidewall that surrounds the bottom board. The bottom board covers the second adhesive layer, and the sidewall covers the side surface of the chip.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: January 23, 2018
    Assignee: XINTEC INC.
    Inventors: Yen-Shih Ho, Hsiao-Lan Yeh, Chia-Sheng Lin, Yi-Ming Chang, Po-Han Lee, Hui-Hsien Wu, Jyun-Liang Wu
  • Publication number: 20170148844
    Abstract: A chip package includes a chip, an adhesive layer, and a dam element. The chip has a sensing area, a first surface, and a second surface that is opposite to the first surface. The sensing area is located on the first surface. The adhesive layer covers the first surface of the chip. The dam element is located on the adhesive layer and surrounds the sensing area. The thickness of the dam element is in a range from 20 ?m to 750 ?m, and the wall surface of the dam element surrounding the sensing area is a rough surface.
    Type: Application
    Filed: November 22, 2016
    Publication date: May 25, 2017
    Inventors: Yen-Shih HO, Hsiao-Lan YEH, Chia-Sheng LIN, Yi-Ming CHANG, Po-Han LEE, Hui-Hsien WU, Jyun-Liang WU, Shu-Ming CHANG, Yu-Lung HUANG, Chien-Min LIN
  • Publication number: 20170148694
    Abstract: A chip package includes a chip, a first adhesive layer, a second adhesive layer, and a protection cap. The chip has a sensing area, a first surface, a second surface that is opposite to the first surface, and a side surface adjacent to the first and second surfaces. The sensing area is located on the first surface. The first adhesive layer covers the first surface of the chip. The second adhesive layer is located on the first adhesive layer, such that the first adhesive layer is between the first surface and the second adhesive layer. The protection cap has a bottom board and a sidewall that surrounds the bottom board. The bottom board covers the second adhesive layer, and the sidewall covers the side surface of the chip.
    Type: Application
    Filed: November 21, 2016
    Publication date: May 25, 2017
    Inventors: Yen-Shih HO, Hsiao-Lan YEH, Chia-Sheng LIN, Yi-Ming CHANG, Po-Han LEE, Hui-Hsien WU, Jyun-Liang WU
  • Publication number: 20170012081
    Abstract: A manufacturing method of a chip package includes the following steps. A patterned solder paste layer is printed on a patterned conductive layer of a wafer. Plural solder balls are disposed on the solder paste layer that is on a first portion of the conductive layer. A reflow process is performed on the solder balls and the solder paste layer. A flux layer converted from a surface of the solder paste layer is cleaned.
    Type: Application
    Filed: June 13, 2016
    Publication date: January 12, 2017
    Inventors: Chia-Lun SHEN, Yi-Ming CHANG, Hsiao-Lan YEH, Yen-Shih HO
  • Publication number: 20160307779
    Abstract: A wafer coating system includes a wafer chuck, a flowing insulating material sprayer and a wafer tilting lifting pin. The wafer chuck has a carrier part and a rotating part, which the carrier part is mounted on the rotating part to carry a wafer, and the rotating part is configured to rotate with a predetermined axis. The flowing insulating material sprayer is above the wafer chuck and configured to spray a flowing insulating material to the wafer, and the wafer tilting lifting pin is configured to form a first acute angle between the wafer and direction of gravity.
    Type: Application
    Filed: April 13, 2016
    Publication date: October 20, 2016
    Inventors: Yu-Tung CHEN, Quan-Qun SU, Chuan-Jin SHIU, Chien-Hui CHEN, Hsiao-Lan YEH, Yen-Shih HO
  • Patent number: 6019849
    Abstract: A number of air actuated valves are added to a conventional apparatus for treating semiconductor wafers with HMDS, hexamethyl-disilazane, vapor to improve the adhesion between the wafers and resist layers. These valves allow for automatic purging of the HMDS vapor from the pipes in the apparatus by dry nitrogen thereby preventing HMDS vapor condensation in the pipes which leads to contamination of the HMDS supply. The valve system prevents any backstreaming of nitrogen gas into the HMDS supply tank.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: February 1, 2000
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chang Chu Yao, Tsun-Ching Lin, Jo-Fei Wang, Hsiao-Lan Yeh
  • Patent number: 5908041
    Abstract: A method and apparatus for cleaning a spray stream nozzle employed in dispensing upon a photoexposed blanket photoresist layer formed over a semiconductor substrate a photoresist developer solution. There is first provided a spray stream nozzle having a minimum of one aperture formed therein. There is then provided through the spray stream nozzle a volume of a photoresist developer solution sufficient to develop a photoexposed blanket photoresist layer formed over a semiconductor substrate placed beneath the spray stream nozzle. Finally, there is provided then through the spray stream nozzle a volume of a solvent which is not susceptible to clogging the spray stream nozzle.
    Type: Grant
    Filed: July 17, 1996
    Date of Patent: June 1, 1999
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Gey-Fung Wei, Tsun-Ching Lin, Jo-Fei Wang, Hsiao-Lan Yeh
  • Patent number: 5763006
    Abstract: A number of air actuated valves are added to a conventional apparatus for treating semiconductor wafers with HMDS, hexamethyl-disilazane, vapor to improve the adhesion between the wafers and resist layers. These valves allow for automatic purging of the HMDS vapor from the pipes in the apparatus by dry nitrogen thereby preventing HMDS vapor condensation in the pipes which leads to contamination of the HMDS supply. The valve system prevents any backstreaming of nitrogen gas into the HMDS supply tank.
    Type: Grant
    Filed: October 4, 1996
    Date of Patent: June 9, 1998
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Chu Yao, Tsun-Ching Lin, Jo-Fei Wang, Hsiao-Lan Yeh