Abstract: Embodiments of the disclosure generally provide methods of forming a capacitor with high capacitance and low leakage as well as a good interface control for thin film transistor (TFT) applications. In one embodiment, a thin film transistor structure includes a capacitor formed in a thin film transistor device. The capacitor further includes a common electrode disposed on a substrate, a dielectric layer formed on the common electrode and a pixel electrode formed on the dielectric layer. An interface protection layer formed between the common electrode and the dielectric layer, or between the dielectric layer and the pixel electrode. A gate insulating layer fabricated by a high-k material may also be utilized in the thin film transistor structure.

Abstract: A method and apparatus for equalized plasma coupling is provided herein. Discontinuity marks, also known as golf tee mura, are eliminated or minimized by biasing or grounding lift pins disposed in openings towards the center of a substrate support. To prevent shorting between a biased or grounded lift pin and the substrate support, lift pins are electrically isolated from the substrate support. The electrical isolation of the lift pin includes coating the lift pins with an electrically insulating material or lining a respective substrate support opening with an electrically insulating material.

Abstract: Embodiments of the disclosure generally provide methods of forming a capacitor with high capacitance and low leakage as well as a good interface control for thin film transistor (TFT) applications. In one embodiment, a thin film transistor structure includes a capacitor formed in a thin film transistor device. The capacitor further includes a common electrode disposed on a substrate, a dielectric layer formed on the common electrode and a pixel electrode formed on the dielectric layer. An interface protection layer formed between the common electrode and the dielectric layer, or between the dielectric layer and the pixel electrode. A gate insulating layer fabricated by a high-k material may also be utilized in the thin film transistor structure.

Abstract: The present invention generally relates to a capacitively coupled plasma (CCP) processing chamber, a manner to reduce or prevent stray capacitance, and a manner to measure plasma conditions within the processing chamber. As CCP processing chambers increase in size, there is a tendency for stray capacitance to negatively impact the process. Additionally, RF ground straps may break. By increasing the spacing between the chamber backing plate and the chamber wall, stray capacitance may be minimized. Additionally, the plasma may be monitored by measuring the conditions of the plasma at the backing plate rather than at the match network. In so measuring, the plasma harmonic data may be analyzed to reveal plasma processing conditions within the chamber.