Patents by Inventor Hsiao-Ling Chiang

Hsiao-Ling Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11934027
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: March 19, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Patent number: 11362085
    Abstract: A high-voltage semiconductor device includes a substrate, a body region, a well region, a bulk region, a source, a drain, an isolation region, a gate structure, and a resistor. The body region and the well region are disposed in the substrate. The bulk region and the source are disposed in the body region. The drain is disposed in the well region. The isolation region is disposed on the well region. The isolation region is disposed between the drain and the source. The gate structure is disposed on the substrate. The gate structure extends onto a portion of the isolation region. The resistor is disposed on the isolation region. The resistor is electrically connected to the bulk region and the drain, or the resistor is electrically connected to the drain and/or the source.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: June 14, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yu-Hao Ho, Hsiao-Ling Chiang, Yueh-Chu Chiang, Yi-Hsiang Huang
  • Publication number: 20220013520
    Abstract: A high-voltage semiconductor device includes a substrate, a body region, a well region, a bulk region, a source, a drain, an isolation region, a gate structure, and a resistor. The body region and the well region are disposed in the substrate. The bulk region and the source are disposed in the body region. The drain is disposed in the well region. The isolation region is disposed on the well region. The isolation region is disposed between the drain and the source. The gate structure is disposed on the substrate. The gate structure extends onto a portion of the isolation region. The resistor is disposed on the isolation region. The resistor is electrically connected to the bulk region and the drain, or the resistor is electrically connected to the drain and/or the source.
    Type: Application
    Filed: July 10, 2020
    Publication date: January 13, 2022
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Yu-Hao HO, Hsiao-Ling CHIANG, Yueh-Chu CHIANG, Yi-Hsiang HUANG
  • Publication number: 20200227342
    Abstract: A semiconductor structure including a substrate, a first well, a field oxide layer, a first conductive line and a second conductive line is provided. The substrate has a first conductivity type. The first well is formed on the substrate and has a second conductivity type. The field oxide layer is disposed on the first well. The first conductive line is formed on the field oxide layer and is in direct contact with the field oxide layer. The second conductive line is formed on the field oxide layer and is in direct contact with the field oxide layer. The first conductive line is spaced apart from the second conductive line.
    Type: Application
    Filed: January 15, 2019
    Publication date: July 16, 2020
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Cheng-Tsung WU, Shin-Cheng LIN, Hsiao-Ling CHIANG, Wen-Hsin LIN
  • Patent number: 10714410
    Abstract: A semiconductor structure including a substrate, a first well, a field oxide layer, a first conductive line and a second conductive line is provided. The substrate has a first conductivity type. The first well is formed on the substrate and has a second conductivity type. The field oxide layer is disposed on the first well. The first conductive line is formed on the field oxide layer and is in direct contact with the field oxide layer. The second conductive line is formed on the field oxide layer and is in direct contact with the field oxide layer. The first conductive line is spaced apart from the second conductive line.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: July 14, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Cheng-Tsung Wu, Shin-Cheng Lin, Hsiao-Ling Chiang, Wen-Hsin Lin
  • Patent number: 9947653
    Abstract: A high-voltage semiconductor device includes a MOS device and a resistor device. The MOS device has a source, a drain, a drain insulation region adjacent to the drain, and a gate adjacent to the source. The resistor device is formed on the drain insulation region and is electrically connected to the drain. The resistor device has a plurality of resistor sections connected in series, and each of the plurality of resistor sections has a curved shape.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: April 17, 2018
    Assignee: VANGAURD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Shin-Cheng Lin, Hsiao-Ling Chiang
  • Publication number: 20170365599
    Abstract: A high-voltage semiconductor device includes a MOS device and a resistor device. The MOS device has a source, a drain, a drain insulation region adjacent to the drain, and a gate adjacent to the source. The resistor device is formed on the drain insulation region and is electrically connected to the drain. The resistor device has a plurality of resistor sections connected in series, and each of the plurality of resistor sections has a curved shape.
    Type: Application
    Filed: June 16, 2016
    Publication date: December 21, 2017
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Shin-Cheng LIN, Hsiao-Ling CHIANG
  • Patent number: 8383767
    Abstract: A protein carrier containing an antigen presenting cell binding domain and a cysteine-rich domain. Also described herein is an immunoconjugate containing the protein carrier with an antigen conjugated to multiple cysteine residues in the cysteine-rich domain, and an immune composition containing the immunoconjugate and an adjuvant, as well as their uses in eliciting immune responses.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: February 26, 2013
    Assignee: Academia Sinica
    Inventors: Jaulang Hwang, Chun-Cheng Lin, Hsiao-Ling Chiang, Fan-Dan Jan, Chiao-En Chen, Chia-Tse Shu
  • Publication number: 20090324619
    Abstract: A protein carrier containing an antigen presenting cell binding domain and a cysteine-rich domain. Also described herein is an immunoconjugate containing the protein carrier with an antigen conjugated to multiple cysteine residues in the cysteine-rich domain, and an immune composition containing the immunoconjugate and an adjuvant, as well as their uses in eliciting immune responses.
    Type: Application
    Filed: June 25, 2009
    Publication date: December 31, 2009
    Applicant: Academia Sinica
    Inventors: Jaulang Hwang, Chun-Cheng Lin, Hsiao-Ling Chiang, Fan-Dan Jan, Chiao-En Chen, Chia-Tse Shu