Patents by Inventor Hsiao-Ling Chiang
Hsiao-Ling Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Patent number: 11362085Abstract: A high-voltage semiconductor device includes a substrate, a body region, a well region, a bulk region, a source, a drain, an isolation region, a gate structure, and a resistor. The body region and the well region are disposed in the substrate. The bulk region and the source are disposed in the body region. The drain is disposed in the well region. The isolation region is disposed on the well region. The isolation region is disposed between the drain and the source. The gate structure is disposed on the substrate. The gate structure extends onto a portion of the isolation region. The resistor is disposed on the isolation region. The resistor is electrically connected to the bulk region and the drain, or the resistor is electrically connected to the drain and/or the source.Type: GrantFiled: July 10, 2020Date of Patent: June 14, 2022Assignee: Vanguard International Semiconductor CorporationInventors: Yu-Hao Ho, Hsiao-Ling Chiang, Yueh-Chu Chiang, Yi-Hsiang Huang
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Publication number: 20220013520Abstract: A high-voltage semiconductor device includes a substrate, a body region, a well region, a bulk region, a source, a drain, an isolation region, a gate structure, and a resistor. The body region and the well region are disposed in the substrate. The bulk region and the source are disposed in the body region. The drain is disposed in the well region. The isolation region is disposed on the well region. The isolation region is disposed between the drain and the source. The gate structure is disposed on the substrate. The gate structure extends onto a portion of the isolation region. The resistor is disposed on the isolation region. The resistor is electrically connected to the bulk region and the drain, or the resistor is electrically connected to the drain and/or the source.Type: ApplicationFiled: July 10, 2020Publication date: January 13, 2022Applicant: Vanguard International Semiconductor CorporationInventors: Yu-Hao HO, Hsiao-Ling CHIANG, Yueh-Chu CHIANG, Yi-Hsiang HUANG
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Publication number: 20200227342Abstract: A semiconductor structure including a substrate, a first well, a field oxide layer, a first conductive line and a second conductive line is provided. The substrate has a first conductivity type. The first well is formed on the substrate and has a second conductivity type. The field oxide layer is disposed on the first well. The first conductive line is formed on the field oxide layer and is in direct contact with the field oxide layer. The second conductive line is formed on the field oxide layer and is in direct contact with the field oxide layer. The first conductive line is spaced apart from the second conductive line.Type: ApplicationFiled: January 15, 2019Publication date: July 16, 2020Applicant: Vanguard International Semiconductor CorporationInventors: Cheng-Tsung WU, Shin-Cheng LIN, Hsiao-Ling CHIANG, Wen-Hsin LIN
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Patent number: 10714410Abstract: A semiconductor structure including a substrate, a first well, a field oxide layer, a first conductive line and a second conductive line is provided. The substrate has a first conductivity type. The first well is formed on the substrate and has a second conductivity type. The field oxide layer is disposed on the first well. The first conductive line is formed on the field oxide layer and is in direct contact with the field oxide layer. The second conductive line is formed on the field oxide layer and is in direct contact with the field oxide layer. The first conductive line is spaced apart from the second conductive line.Type: GrantFiled: January 15, 2019Date of Patent: July 14, 2020Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Cheng-Tsung Wu, Shin-Cheng Lin, Hsiao-Ling Chiang, Wen-Hsin Lin
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Patent number: 9947653Abstract: A high-voltage semiconductor device includes a MOS device and a resistor device. The MOS device has a source, a drain, a drain insulation region adjacent to the drain, and a gate adjacent to the source. The resistor device is formed on the drain insulation region and is electrically connected to the drain. The resistor device has a plurality of resistor sections connected in series, and each of the plurality of resistor sections has a curved shape.Type: GrantFiled: June 16, 2016Date of Patent: April 17, 2018Assignee: VANGAURD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Shin-Cheng Lin, Hsiao-Ling Chiang
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Publication number: 20170365599Abstract: A high-voltage semiconductor device includes a MOS device and a resistor device. The MOS device has a source, a drain, a drain insulation region adjacent to the drain, and a gate adjacent to the source. The resistor device is formed on the drain insulation region and is electrically connected to the drain. The resistor device has a plurality of resistor sections connected in series, and each of the plurality of resistor sections has a curved shape.Type: ApplicationFiled: June 16, 2016Publication date: December 21, 2017Applicant: Vanguard International Semiconductor CorporationInventors: Shin-Cheng LIN, Hsiao-Ling CHIANG
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Patent number: 8383767Abstract: A protein carrier containing an antigen presenting cell binding domain and a cysteine-rich domain. Also described herein is an immunoconjugate containing the protein carrier with an antigen conjugated to multiple cysteine residues in the cysteine-rich domain, and an immune composition containing the immunoconjugate and an adjuvant, as well as their uses in eliciting immune responses.Type: GrantFiled: June 25, 2009Date of Patent: February 26, 2013Assignee: Academia SinicaInventors: Jaulang Hwang, Chun-Cheng Lin, Hsiao-Ling Chiang, Fan-Dan Jan, Chiao-En Chen, Chia-Tse Shu
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Publication number: 20090324619Abstract: A protein carrier containing an antigen presenting cell binding domain and a cysteine-rich domain. Also described herein is an immunoconjugate containing the protein carrier with an antigen conjugated to multiple cysteine residues in the cysteine-rich domain, and an immune composition containing the immunoconjugate and an adjuvant, as well as their uses in eliciting immune responses.Type: ApplicationFiled: June 25, 2009Publication date: December 31, 2009Applicant: Academia SinicaInventors: Jaulang Hwang, Chun-Cheng Lin, Hsiao-Ling Chiang, Fan-Dan Jan, Chiao-En Chen, Chia-Tse Shu