Patents by Inventor Hsiao Liu
Hsiao Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240379841Abstract: A semiconductor device includes a first well region having the first conductivity type and a second well region having the second conductivity type formed in a substrate having the first conductivity type. An isolation component and a third well region are formed in the second well region. The third well region has the first conductivity type and is in contact with the bottom surface of the isolation component. A first doping region is formed in the first well region and a second doping region is formed in the second well region. The first and second doping regions have the second conductivity type and are disposed at opposite sides of the gate structure. The interface between the first well region and the second well region is positioned between the isolation component and the first doping region. The interface is separated from the third well region by a lateral distance.Type: ApplicationFiled: May 8, 2023Publication date: November 14, 2024Applicant: Vanguard International Semiconductor CorporationInventors: Tse-Hsiao LIU, Po-Hao CHIU, Nai-Lun CHENG, Pi-Kuang CHUANG, Chih-Hung LIN, Ching-Yi HSU
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Publication number: 20240128313Abstract: A method includes providing a substrate, forming a patterned hard mask layer over the substrate, etching the patterned hard mask layer to form a hole that penetrates the patterned hard mask layer, forming a barrier portion in the hole, removing the patterned hard mask layer, and forming a gate structure over the substrate. Formation of the gate structure includes forming a dielectric body portion on the substrate. The barrier portion that is thicker than the dielectric body portion adjoins one end of the dielectric body portion. The dielectric body portion and the barrier portion are collectively referred to as a gate dielectric layer. Formation of the gate structure further includes forming a gate electrode on the gate dielectric layer and forming gate spacers on opposite sidewalls of the gate electrode. During formation of the gate spacers, a portion of the barrier portion is removed to form a recessed corner.Type: ApplicationFiled: October 17, 2022Publication date: April 18, 2024Applicant: Vanguard International Semiconductor CorporationInventors: Tse-Hsiao LIU, Chih-Wei LIN, Po-Hao CHIU, Pi-Kuang CHUANG, Ching-Yi HSU
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Publication number: 20230060729Abstract: The present disclosure is related to a power module. The power module includes first fasteners and power devices. The power devices are adjacently disposed and locked by the first fasteners. Each of the power devices packages a power electronic therein. Each of the power devices includes a first extending portion. The first extending portion extends from a side of the power device. The first extending portion includes at least one first curved opening for receiving the first fastener. The first curved openings are adjacently disposed to form a first inserting hole. The first fastener passes through the first inserting hole.Type: ApplicationFiled: August 30, 2022Publication date: March 2, 2023Inventors: Chia-Chi WU, Lian-An JIAN, Cheng-Yu SHEN, Chun-Hong CHEN, Hung-Hsiao LIU
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Patent number: 11387361Abstract: A method for forming a semiconductor structure includes: forming a first gate structure in a predetermined low-potential region of a substrate and a second gate structure in a predetermined high-potential region of the substrate; sequentially forming a first dielectric layer and a second dielectric layer covering the first gate structure and the second gate structure; forming a portion of a third dielectric layer along sidewalls of the second gate structure and on the second dielectric layer; and etching the first dielectric layer and the second dielectric layer with the portion of the third dielectric layer as an etching hard mask to form a first composite spacer covering sidewalls of the first gate structure, and a second composite spacer covering the sidewalls of the second gate structure, wherein a width of the first composite spacer is less than a width of the second composite spacer.Type: GrantFiled: February 6, 2020Date of Patent: July 12, 2022Assignee: Vanguard International Semiconductor CorporationInventors: Chin-Hsiu Huang, Tse-Hsiao Liu, Pao-Hao Chiu, Chih-Cherng Liao, Ching-Yi Hsu
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Publication number: 20210249536Abstract: A method for forming a semiconductor structure includes: forming a first gate structure in a predetermined low-potential region of a substrate and a second gate structure in a predetermined high-potential region of the substrate; sequentially forming a first dielectric layer and a second dielectric layer covering the first gate structure and the second gate structure; forming a portion of a third dielectric layer along sidewalls of the second gate structure and on the second dielectric layer; and etching the first dielectric layer and the second dielectric layer with the portion of the third dielectric layer as an etching hard mask to form a first composite spacer covering sidewalls of the first gate structure, and a second composite spacer covering the sidewalls of the second gate structure, wherein a width of the first composite spacer is less than a width of the second composite spacer.Type: ApplicationFiled: February 6, 2020Publication date: August 12, 2021Applicant: Vanguard International Semiconductor CorporationInventors: Chin-Hsiu HUANG, Tse-Hsiao LIU, Pao-Hao CHIU, Chih-Cherng LIAO, Ching-Yi HSU
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Patent number: 9978864Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a first conductive type well region; a gate structure; a lightly-doped drain region and a lightly-doped source region disposed at two opposite sides of the gate structure; a second conductive type first doped region disposed in the lightly-doped drain region, wherein the doping concentration of the second conductive type first doped region is less than the doping concentration of the lightly-doped drain region; a heavily-doped source region disposed in the lightly-doped source region; and a heavily-doped drain region disposed in the second conductive type first doped region. The present disclosure also provides a method for manufacturing the semiconductor device.Type: GrantFiled: December 3, 2015Date of Patent: May 22, 2018Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Tse-Hsiao Liu, Sing-Lin Wu, Chung-Hsuan Wang, Yung-Lung Chou, Chia-Hao Lee, Chih-Cherng Liao
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Publication number: 20170162691Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a first conductive type well region; a gate structure; a lightly-doped drain region and a lightly-doped source region disposed at two opposite sides of the gate structure; a second conductive type first doped region disposed in the lightly-doped drain region, wherein the doping concentration of the second conductive type first doped region is less than the doping concentration of the lightly-doped drain region; a heavily-doped source region disposed in the lightly-doped source region; and a heavily-doped drain region disposed in the second conductive type first doped region. The present disclosure also provides a method for manufacturing the semiconductor device.Type: ApplicationFiled: December 3, 2015Publication date: June 8, 2017Applicant: Vanguard International Semiconductor CorporationInventors: Tse-Hsiao LIU, Sing-Lin WU, Chung-Hsuan WANG, Yung-Lung CHOU, Chia-Hao LEE, Chih-Cherng LIAO
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Publication number: 20150207166Abstract: A fuel cell for improving flow field uniformity and reducing gas pressure loss includes a fuel cell stack and a gas input unit. The gas input unit has a gas input passage, an input port, an input baffle plate and at least one perforated plate. An end of the gas input passage is connected to an end of the fuel cell stack. The input port is disposed on another end of the gas input passage. The input baffle plate is disposed in the gas input passage and located in front of the input port, and a gap exists between the input baffle plate and the input port. The perforated plate is disposed between the input baffle plate and the fuel cell stack.Type: ApplicationFiled: March 11, 2014Publication date: July 23, 2015Applicant: NATIONAL TSING HUA UNIVERSITYInventors: Che-Wun Hong, Hung-Hsiao Liu, Angel Giancarlo Miranda Canales
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Publication number: 20150198147Abstract: A fuel cell incorporating a wind power generating device includes a fuel cell stack, a gas input unit and a wind power generating device. The gas input unit, configured to provide an input gas, includes a gas diffusion path and an inlet. The cell stack is connected to an end of the gas diffusion path. The inlet is disposed on another end of the gas diffusion path. The wind power generating device includes at least one first fan and a first electric generator. The at least one first fan is disposed in the gas diffusion path and is actuated by the input gas to drive the electric generator for generating electricity from wind power.Type: ApplicationFiled: March 6, 2014Publication date: July 16, 2015Applicant: National Tsing Hua UniversityInventors: Che-Wun Hong, Hung-Hsiao Liu
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Publication number: 20140137164Abstract: An In-Flight Entertainment system is provided with a server unit and a display unit. The server unit is configured to maintain digital content. The display unit is configured to connect to the server unit through a wired network for receiving and presenting the digital content. The display unit further includes a wireless module for wirelessly transmitting the digital content received from the server unit to be presented by a first portable device.Type: ApplicationFiled: November 15, 2012Publication date: May 15, 2014Applicant: DELTA NETWORKS, INC.Inventors: Hsi-Ching YANG, Ta LIN, Chien-Heng WU, Jyh-Ming KUO, Tsen-Hsiao LIU
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Patent number: 8610523Abstract: The invention is a magnetic fix structure that applies on a projection device. The magnetic fix structure includes a first magnetic connector set and a second magnetic connector set, and the projection device includes a projection module housing and a power module housing. The first magnetic connector set and the second magnetic connector set are disposed on the projection module housing and the power module housing respectively. Therefore, through the attraction between the first magnetic connector set and the second magnetic connector set, the power module housing can be fixed onto the projection module housing.Type: GrantFiled: January 12, 2012Date of Patent: December 17, 2013Assignee: Delta Electronics, Inc.Inventors: Tsang-Hsing Ku, Kuang-Hsiao Liu
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Publication number: 20120194977Abstract: A portable electronic device includes a main portion, a display portion and a support arm. The main portion has an accommodation area on an upper surface thereof. The support arm is pivotally connected with the main portion at a first end and pivotally connected with the display portion at an opposite second end such that the display portion is rotatable relative to the main portion by means of the support arm. When the display portion is laid against the main portion, the support arm is disposed within the accommodation area.Type: ApplicationFiled: July 29, 2011Publication date: August 2, 2012Applicant: Quanta Computer Inc.Inventors: Chih-Hsiao Liu, Tsung-Ju Chiang, Li-Ke Chen, Chun-Yi Yuan
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Publication number: 20120188034Abstract: The invention is a magnetic fix structure that applies on a projection device. The magnetic fix structure includes a first magnetic connector set and a second magnetic connector set, and the projection device includes a projection module housing and a power module housing. The first magnetic connector set and the second magnetic connector set are disposed on the projection module housing and the power module housing respectively. Therefore, through the attraction between the first magnetic connector set and the second magnetic connector set, the power module housing can be fixed onto the projection module housing.Type: ApplicationFiled: January 12, 2012Publication date: July 26, 2012Applicant: DELTA ELECTRONICS, INC.Inventors: Tsang-Hsing Ku, Kuang-Hsiao Liu
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Patent number: 8085547Abstract: An electronic elements carrier includes a body, at least an electronic element and a filler. The body includes a substrate having a plate and a dam formed on the peripheral of plate, a conductive layer mounted on a surface of the dam, and at least a cavity defined by the plate and the dam of the substrate. The electronic element is disposed in the cavity of the body. The filler is received in the cavity of the substrate for encapsulating, sealing and protecting the electronic element.Type: GrantFiled: November 30, 2007Date of Patent: December 27, 2011Assignee: Hon Hai Precision Industry Co., Ltd.Inventors: Ying-Cheng Wu, Kun-Hsiao Liu
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Patent number: 7521770Abstract: An image capturing device includes an image sensor package and a lens module aligned with the image sensor package. The image sensor package includes a substrate, at least one passive component, an insulative layer, and an image sensor. The substrate has a surface facing an object side of the image capturing device, the surface defines a cavity therein. The at least one passive component is disposed within the cavity and electrically connected to the substrate. The insulative layer is received in the cavity and encases the at least one passive component. The image sensor is disposed on the insulative layer and electrically connected to the substrate. The holder has an end connecting with the barrel and an opposite end secured on the substrate.Type: GrantFiled: September 27, 2007Date of Patent: April 21, 2009Assignee: Hon Hai Precision Industry Co., Ltd.Inventors: Ying-Cheng Wu, Kun-Hsiao Liu
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Publication number: 20080265350Abstract: An image capturing device includes an image sensor package and a lens module aligned with the image sensor package. The image sensor package includes a substrate, at least one passive component, an insulative layer, and an image sensor. The substrate has a surface facing an object side of the image capturing device, the surface defines a cavity therein. The at least one passive component is disposed within the cavity and electrically connected to the substrate. The insulative layer is received in the cavity and encases the at least one passive component. The image sensor is disposed on the insulative layer and electrically connected to the substrate. The holder has an end connecting with the barrel and an opposite end secured on the substrate.Type: ApplicationFiled: September 27, 2007Publication date: October 30, 2008Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: YING-CHENG WU, KUN-HSIAO LIU
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Publication number: 20080266822Abstract: An electronic elements carrier includes a body, at least an electronic element and a filler. The body includes a substrate having a plate and a dam formed on the peripheral of plate, a conductive layer mounted on a surface of the dam, and at least a cavity defined by the plate and the dam of the substrate. The electronic element is disposed in the cavity of the body. The filler is received in the cavity of the substrate for encapsulating, sealing and protecting the electronic element.Type: ApplicationFiled: November 30, 2007Publication date: October 30, 2008Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: YING-CHENG WU, KUN-HSIAO LIU
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Publication number: 20080251875Abstract: An exemplary semiconductor package includes a substrate, at least one passive component, an insulative layer and a chip. The substrate defines a cavity therein. The at least one passive component is disposed within the cavity, and is electrically connected to the substrate. The insulative layer is received in the cavity, and encases the at least one passive component. The chip is disposed on the insulative layer, and is electrically connected to the substrate. The semiconductor package packaging the at least one passive component within the cavity and under the chip can improve a space usage thereof, thus a packaging scale of the semiconductor package could be reduced.Type: ApplicationFiled: September 5, 2007Publication date: October 16, 2008Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: YING-CHENG WU, KUN-HSIAO LIU
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Publication number: 20070077959Abstract: This provides a system to emit a plurality of electronic signals, sent by a person(s) trapped by some disaster, such as collapse of building, earthquake, flood, etc. The plurality of signals provides a better chance that rescuers will receive at least one signal.Type: ApplicationFiled: September 19, 2005Publication date: April 5, 2007Inventors: Edward Newman, Sean Newman, Benjamin Newman, Richard Bizar, Hsiao Liu
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Publication number: 20070028993Abstract: An elastic woven tape is disclosed as being composed of at least two kinds of tape sections, each of which having a respectively different elongation and/or modulus, and formed by alternating and continuous integration of these two kinds of tape sections by weaving. The weaving method of the said elastic woven tape includes controlling the changes in the degrees of elasticity provided by elastic threads for the woven tape in mechanized weaving through the control of the feeding speeds of the elastic threads. The advantageous effects of this invention lie in the production of a woven tape composed of tape sections respectively with larger elongation but smaller modulus and with smaller elongation but larger modulus by means of their alternating and continuous integration by weaving, which simplifies the post-weaving operation and improves production efficiency.Type: ApplicationFiled: September 25, 2006Publication date: February 8, 2007Inventors: Ah Lam, Hsiao Liu