Patents by Inventor HSIAO LU CHEN

HSIAO LU CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240105849
    Abstract: A method for forming a semiconductor structure is provided. The method for forming the semiconductor structure includes forming a fin structure over a substrate in a first direction, forming a first gate stack, a second gate stack and a third gate stack across the fin structure, removing the first gate stack to form a trench, depositing a cutting structure in the trench, and forming a first contact plug between the cutting structure and the second gate stack and a second contact plug between the second gate stack and the third gate stack. The fin structure is cut into two segments by the trench. A first dimension of the first contact plug in the first direction is greater than a second dimension of the second contact plug in the first direction.
    Type: Application
    Filed: February 10, 2023
    Publication date: March 28, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Da-Zhi ZHANG, Chun-An LU, Chung-Yu CHIANG, Po-Nien CHEN, Hsiao-Han LIU, Jhon-Jhy LIAW, Chih-Yung LIN
  • Publication number: 20240076307
    Abstract: Provided are compounds of Formula Ir(LA)x(LC)y wherein: ligand LA has Formula I? ?and ligand LC has Formula II?
    Type: Application
    Filed: October 10, 2023
    Publication date: March 7, 2024
    Applicant: Universal Display Corporation
    Inventors: Wei-Chun SHIH, Zhiqiang JI, Pierre-Luc T. BOUDREAULT, Hsiao-Fan CHEN, Tongxiang LU
  • Publication number: 20240072033
    Abstract: A bonding and transferring method for die package structures is provided, including providing a die package structure which has a positioning adhesive disposed thereon, and providing a vibration base having at least one cavity corresponding to the positioning adhesive. By alignment of the positioning adhesive and the cavity, the die package structure can be positioned into the vibration base. A target substrate is further provided and bonded with the vibration base having the die package structure disposed thereon through a metal material. And a laser process is then performed to melt the metal material. At last, the vibration base and the positioning adhesive are removed so the die package structure is successfully bonded and transferred onto the target substrate. By employing the proposed process method of the present invention, rapid mass transfer result is accomplished, and the packaging yield of vertical light emitting diode die package structures is optimized.
    Type: Application
    Filed: February 7, 2023
    Publication date: February 29, 2024
    Applicant: Ingentec Corporation
    Inventors: Hsiao Lu Chen, AI SEN LIU, HSIANG AN FENG, YA LI CHEN
  • Publication number: 20240072013
    Abstract: A vertical light emitting diode die packaging method is provided, including a plurality of following steps. At first, a plurality of drill hole is formed in a substrate and a first metal material is used to fill the drill holes. Next, disposing and fixing a plurality of vertical light emitting diode die on the substrate through a second metal material, and a transparent glue is used to cover thereon. A laser process is then employed to dissolve the transparent glue for forming ditches. And, a conductive liquid is applied to fill the ditches and an insulating glue is provided to embrace and encapsulate the vertical light emitting diode dies. By employing the packaging method of the present invention, the current external wire bonding process can be effectively replaced, thereby die size miniaturization as well as packaging yield of the vertical light emitting diode dies are believed to be optimized.
    Type: Application
    Filed: February 7, 2023
    Publication date: February 29, 2024
    Applicant: Ingentec Corporation
    Inventors: HSIAO LU CHEN, AI SEN LIU, HSIANG AN FENG
  • Publication number: 20240071872
    Abstract: A via-filling method of a TGV substrate includes steps: filling a plurality of metal balls into a plurality of vias of the TGV substrate; using a heating process to melt the plurality of metal balls to form a liquid-state metal; and cooling down the liquid-state metal to form a solid-state metal inside the plurality of vias. Because the method needn't use solvents or fluxes, the solid-state metal inside the plurality of vias have better electric conductivity.
    Type: Application
    Filed: February 7, 2023
    Publication date: February 29, 2024
    Applicant: Ingentec Corporation
    Inventors: Hsiao Lu Chen, AI SEN LIU, HSIANG AN FENG, YA LI CHEN
  • Publication number: 20240008170
    Abstract: An LED circuit board structure includes first color LEDs, second color LEDs, third color LEDs, a carrier board, first testing wires, first connecting wires, second testing wires and second connecting wires. Each of the first testing wire is located at the carrier board and electrically connects two first color LEDs in a pixel-front-side-pattern region in parallel. The first connecting wire electrically connects two first testing wires in adjacent two pixel-front-side-pattern regions. Each of the second testing wire is located at the carrier board and electrically connects two second color LEDs in a pixel-front-side-pattern region in parallel. The second connecting wire electrically connects two second testing wires in adjacent two pixel-front-side-pattern regions.
    Type: Application
    Filed: September 16, 2022
    Publication date: January 4, 2024
    Inventors: Yi-Chuan HUANG, Hsiao-Lu CHEN, Ai-Sen LIU
  • Publication number: 20240006557
    Abstract: An LED circuit board structure includes first color LEDs, second color LEDs, third color LEDs, integrated circuit chips, a carrier board, first P-type pads, first color pads, first testing wires and first connecting wires. One of the first P-type pads is disposed at a pixel-front-side-pattern region for mounting a first P-type electrode. One of the first color pads is disposed at the pixel-front-side-pattern region for mounting a first pin of the integrated circuit chip. The first color pad electrically connects to the first P-type pad. A first testing wire is disposed at the pixel-front-side-pattern region and extends from the first P-type pad or the first color pad. The first connecting wire electrically connects two first testing wires in adjacent two pixel-front-side-pattern regions in parallel.
    Type: Application
    Filed: November 21, 2022
    Publication date: January 4, 2024
    Inventors: Yi-Chuan HUANG, Hsiao-Lu CHEN, Ai-Sen LIU
  • Publication number: 20230369296
    Abstract: A magnetic LED die transferring device includes a substrate, a plurality of magnetic members and a vibrating mechanism. The substrate includes a plurality of die locating areas arranged in intervals, and each of the die locating areas includes a locating surface. Each of the magnetic members corresponds to each of the die locating areas and includes an alignment N-pole and an alignment S-pole. The vibrating mechanism is coupled to the substrate. The N-pole and the S-pole of each of the magnetic LED dice are used to be attracted by each of the alignment N-poles and each of the alignment S-poles, respectively, to allow each of the magnetic LED dice to be transferred and aligned to each of the die locating areas.
    Type: Application
    Filed: March 26, 2023
    Publication date: November 16, 2023
    Inventors: Ai-Sen LIU, Hsiao-Lu CHEN, Yi-Chuan HUANG, Hsiang-An FENG
  • Publication number: 20230170434
    Abstract: A method for fabricating a vertical light-emitting diode includes: providing a growth substrate, wherein an epitaxial layer is formed on the growth substrate; forming a metal combined substrate on the epitaxial layer, wherein the metal combined substrate comprises two first metal layers and a second metal layer therebetween, one of the first metal layers is close to the epitaxial layer, and another of the first metal layers is far away from the epitaxial layer; removing the growth substrate; forming a contact metal layer on the epitaxial layer; and removing the second metal layer and the first metal layer far away from the epitaxial layer and leaving the first metal layer close to the epitaxial layer. The vertical light-emitting diode, fabricated by the method, has a thinner thickness, a stronger mechanical strength, a higher light intensity, and a better heat-dissipating effect.
    Type: Application
    Filed: June 28, 2022
    Publication date: June 1, 2023
    Inventors: AI SEN LIU, HSIANG AN FENG, HSIAO LU CHEN, YI CHUAN HUANG