Patents by Inventor Hsiao-Lung Chu

Hsiao-Lung Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6799909
    Abstract: A method of providing fully automated processing of a Split Lot of wafers to manufacture semiconductor devices is provided. The method processes a test Lot of wafers with a production Lot. Processing of both Lots continue as a single Lot along the production processing path up to a split condition process. Processing of the production Lot is put on hold until the alternate processing or test Lot processing is completed. The two Lots are then merged and processed according to the original predefined process steps continue on both Lots.
    Type: Grant
    Filed: April 4, 2003
    Date of Patent: October 5, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih Pang Liu, Hao Ming Gong, Wei Yao Lin, Hsien Jung Hsu, Hsiao Lung Chu, I-Chun Chen, Tse An Chou, Larry Jann
  • Patent number: 6775584
    Abstract: A new software support package is provided that monitors tool status and scheduling requirements in a semiconductor manufacturing environment. A multiplicity of tools interfaces with a Manufacturing Execution system (MES) that is a functional component of the Operation and supervision integrated MES user Interface (OMI). A User Interface (UI) function, which is also part of the OMI, interfaces between a multiplicity of users (of the OMI functions) and the MES sub-component of the OMI system.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: August 10, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chien-Chung Huang, Hsiao-Lung Chu, Yu-Feng Huang
  • Publication number: 20040115842
    Abstract: A method of providing fully automated processing of a Split Lot of wafers to manufacture semiconductor devices is provided. The method processes a test Lot of wafers with a production Lot. Processing of both Lots continue as a single Lot along the production processing path up to a split condition process. Processing of the production Lot is put on hold until the alternate processing or test Lot processing is completed. The two Lots are then merged and processed according to the original predefined process steps continue on both Lots.
    Type: Application
    Filed: April 4, 2003
    Publication date: June 17, 2004
    Inventors: Chih Pang Liu, Hao Ming Gong, Wei Yao Lin, Hsien Jung Hsu, Hsiao Lung Chu, I-Chun Chen, Tse An Chou, Larry Jann