Abstract: An encryption and signature device for AI model protection is provided. The encryption and signature device for AI model protection includes a key derivation unit, a model encryption unit, a model password encryption unit, an image generation unit and a signature unit. The key derivation unit is configured to derive a model key according to a model password and a derivation function. The model encryption unit is configured to encrypt an AI model according to the model key to generate an encrypted AI model. The model password encryption unit is configured to encrypt the model password to generate an encrypted model password. The image generation unit is configured to generate an image file according to the encrypted model password and the encrypted AI model. The signature unit is configured to sign the image file according to a private key to obtain a signed image file.

Abstract: A headphone driver is used to drive a headphone apparatus, which includes a first differential driver, a first positive output terminal, a first negative output terminal, and a second negative output terminal. The first positive output terminal is connected to the first terminal. A switch unit is disposed on a feedback path at the first negative output terminal and the second negative output terminal, to enable the first/second negative output terminal in feedback as a close loop to output to the third/fourth terminal and disable the second/first negative output terminal at a first/second operation state. The first differential driver includes a first positive voltage driving circuit, a first negative voltage driving circuit, and a second negative voltage driving circuit, respectively providing the first positive output terminal, the first negative output terminal, and the second negative output terminal.

Abstract: A headphone driver is used to drive a headphone apparatus, which includes a first differential driver, a first positive output terminal, a first negative output terminal, and a second negative output terminal. The first positive output terminal is connected to the first terminal. A switch unit is disposed on a feedback path at the first negative output terminal and the second negative output terminal, to enable the first/second negative output terminal in feedback as a close loop to output to the third/fourth terminal and disable the second/first negative output terminal at a first/second operation state. The first differential driver includes a first positive voltage driving circuit, a first negative voltage driving circuit, and a second negative voltage driving circuit, respectively providing the first positive output terminal, the first negative output terminal, and the second negative output terminal.

Abstract: A voltage reference generator which can be automatically calibrated has a first mode and a second mode. The voltage reference generator provides a bandgap reference voltage with a voltage reference node having a capacitance. Calibration logic, which can be on the same integrated circuit device as the voltage reference generator, executes a calibration sequence including enabling the voltage reference generator in the first mode to produce a voltage on the voltage reference node, holding the voltage by the capacitance, and then enabling the voltage reference generator in the second mode and calibrating the voltage reference generator in the second mode relative to the voltage held on the voltage reference node, to provide the bandgap reference voltage.

Abstract: A headphone driver includes first and second differential driver differential driver. The first differential driver has a first positive output terminal and a first negative output terminal. The first positive output terminal is coupled to a first terminal of a first speaker. The first negative output terminal is virtually shorted to a reference voltage through a first feedback circuit in the first differential driver. The second differential driver has a second positive output terminal and a second negative output terminal. The second positive output terminal is coupled to a first terminal of a second speaker, wherein the second negative output terminal is virtually shorted to the reference voltage through a second feedback circuit in the first differential driver. The first negative terminal and the second negative terminal are connected to a common line, which is to be further connected to second terminals of the first speaker and the second speaker.

Abstract: A voltage reference generator which can be automatically calibrated has a first mode and a second mode. The voltage reference generator provides a bandgap reference voltage with a voltage reference node having a capacitance. Calibration logic, which can be on the same integrated circuit device as the voltage reference generator, executes a calibration sequence including enabling the voltage reference generator in the first mode to produce a voltage on the voltage reference node, holding the voltage by the capacitance, and then enabling the voltage reference generator in the second mode and calibrating the voltage reference generator in the second mode relative to the voltage held on the voltage reference node, to provide the bandgap reference voltage.

Abstract: A system for reducing a transition short circuit current in an inverter circuit includes a first inverter and a variable resistor set. The first inverter includes a first output node, a first PMOS device, and a first NMOS device. The variable resistor set biases the first inverter such that the first PMOS device is switched at a first time and the first NMOS device is switched at a second time, thereby substantially reducing the transition short circuit current. A method for reducing the transition short circuit current and a buffer circuit also are described.

Abstract: A system for reducing a transition short circuit current in an inverter circuit includes a first inverter and a variable resistor set. The first inverter includes a first output node, a first PMOS device, and a first NMOS device. The variable resistor set biases the first inverter such that the first PMOS device is switched at a first time and the first NMOS device is switched at a second time, thereby substantially reducing the transition short circuit current. A method for reducing the transition short circuit current and a buffer circuit also are described.

Abstract: A low power latch sense amplifier for electrically being coupled to a bit line of a memory cell array is disclosed. The low power latch sense amplifier comprises a common gate sense amplifier and an activated latch register. The common gate sense amplifier comprising a current source and a biased metal-oxide semiconductor is applied for sensing the current of the bit line. The current source and the biased MOS are coupled to a first node, and the common gate sense amplifier outputs a sensing signal at the first node. The activated latch register comprises a first clock signal-synchronized inverter which includes a first inverter and a first switch. The first inverter responds to the sensing signal, and the first inverter outputs a first inverter output signal. The first switch is controlled by a first set of control signal, and the first inverter output signal is corresponding to the sensing signal when the first switch is turned on.

Abstract: A low power latch sense amplifier for electrically being coupled to a bit line of a memory cell array is disclosed. The low power latch sense amplifier comprises a source follower sense amplifier and an activated latch register. The source follower sense amplifier comprising a current source and a biased metal-oxide semiconductor is applied for sensing the current of the bit line. The current source and the biased MOS are coupled to a first node, and the source follower sense amplifier outputs a sensing signal at the first node. The activated latch register comprises a first clock signal-synchronized inverter which includes a first inverter and a first switch. The first inverter responses to the sensing signal, and the first inverter outputs a first inverter output signal. The first switch is controlled by a first set of control signal, and the first inverter output signal is corresponding to the sensing signal when the first switch is turned on.

Abstract: A method of reducing the capacitance of a conductive layer and a semiconductor obtained thereby. In the method, a well region is formed below the isolation, adjacent to it, an in a floating form. The well region has a dopant type different than the dopant type of the substrate. A depletion region can be formed at the interface between the floating well and the substrate. By connecting the capacitance of the depletion region and the parasitic capacitance generated between the conductive layer and the floating well in series, the total parasitic capacitance of the conductive layer can be reduced so as to increase the operational speed of the device.

Abstract: A method of reducing the capacitance of a conductive layer and a semiconductor obtained thereby. In the method, a well region is formed below the isolation, adjacent to it, and in a floating form. The well region has a dopant type different than the dopant type of the substrate. A depletion region can be formed at the interface between the floating well and the substrate. By connecting the capacitance of the depletion region and the parasitic capacitance generated between the conductive layer and the floating well in series, the total parasitic capacitance of the conductive layer can be reduced so as to increase the operational speed of the device.