Patents by Inventor Hsiao-Pei Lin
Hsiao-Pei Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11688683Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a semiconductor device, an interconnect structure, a capacitor, and a plurality of pads. The semiconductor device is disposed at the substrate. The interconnect structure is disposed on the substrate and electrically connected to the semiconductor device. The capacitor is disposed on the interconnect structure and electrically connected to the interconnect structure. The capacitor includes a first electrode, a second electrode covering a top surface and a sidewall of the first electrode, and an insulating layer disposed between the first electrode and the second electrode. The plurality of pads are disposed on the interconnect structure and electrically connected to the interconnect structure, wherein at least one of the plurality of pads is electrically connected to the capacitor.Type: GrantFiled: January 11, 2022Date of Patent: June 27, 2023Assignee: Powerchip Semiconductor Manufacturing CorporationInventors: Hsiao-Pei Lin, Shih-Ping Lee, Cheng-Zuo Han
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Patent number: 11367728Abstract: Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer, and a capacitor. The first transistor and the second transistor are disposed on a substrate. Each of the first and second transistors includes a gate disposed on the substrate and two source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and the second transistors. The conductive layer is disposed above the first transistor and the second transistor, and includes a circuit portion, a first dummy portion, and a second dummy portion, wherein the circuit portion is electrically connected to the first transistor and the second transistor, the first dummy portion is located above the first transistor, and the second dummy portion is located above the second transistor. The capacitor is disposed on the substrate and located between the first dummy portion and the second dummy portion.Type: GrantFiled: October 21, 2020Date of Patent: June 21, 2022Assignee: Powerchip Semiconductor Manufacturing CorporationInventors: Shih-Ping Lee, Shyng-Yeuan Che, Hsiao-Pei Lin, Po-Yi Wu, Kuo-Fang Huang
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Patent number: 11367727Abstract: Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer and a capacitor. Each of the first and second transistors includes a gate disposed on the substrate and source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The conductive layer is disposed above the first and second transistors and includes a circuit portion electrically connected to the first and second transistors and a dummy portion located above the isolation structure. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extension portions extend from the body portion to the source/drain regions of the first and the second transistors, respectively. The first and second extension portions are disposed between the circuit portion and the dummy portion, respectively.Type: GrantFiled: October 21, 2020Date of Patent: June 21, 2022Assignee: Powerchip Semiconductor Manufacturing CorporationInventors: Shih-Ping Lee, Shyng-Yeuan Che, Hsiao-Pei Lin, Po-Yi Wu, Kuo-Fang Huang
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Publication number: 20220139825Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a semiconductor device, an interconnect structure, a capacitor, and a plurality of pads. The semiconductor device is disposed at the substrate. The interconnect structure is disposed on the substrate and electrically connected to the semiconductor device. The capacitor is disposed on the interconnect structure and electrically connected to the interconnect structure. The capacitor includes a first electrode, a second electrode covering a top surface and a sidewall of the first electrode, and an insulating layer disposed between the first electrode and the second electrode. The plurality of pads are disposed on the interconnect structure and electrically connected to the interconnect structure, wherein at least one of the plurality of pads is electrically connected to the capacitor.Type: ApplicationFiled: January 11, 2022Publication date: May 5, 2022Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Hsiao-Pei Lin, Shih-Ping Lee, Cheng-Zuo Han
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Patent number: 11264322Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a semiconductor device, an interconnect structure, a capacitor, and a plurality of pads. The semiconductor device is disposed at the substrate. The interconnect structure is disposed on the substrate and electrically connected to the semiconductor device. The capacitor is disposed on the interconnect structure and electrically connected to the interconnect structure. The capacitor includes a first electrode, a second electrode covering a top surface and a sidewall of the first electrode, and an insulating layer disposed between the first electrode and the second electrode. The plurality of pads are disposed on the interconnect structure and electrically connected to the interconnect structure, wherein at least one of the plurality of pads is electrically connected to the capacitor.Type: GrantFiled: May 19, 2020Date of Patent: March 1, 2022Assignee: Powerchip Semiconductor Manufacturing CorporationInventors: Hsiao-Pei Lin, Shih-Ping Lee, Cheng-Zuo Han
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Publication number: 20210320062Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a semiconductor device, an interconnect structure, a capacitor, and a plurality of pads. The semiconductor device is disposed at the substrate. The interconnect structure is disposed on the substrate and electrically connected to the semiconductor device. The capacitor is disposed on the interconnect structure and electrically connected to the interconnect structure. The capacitor includes a first electrode, a second electrode covering a top surface and a sidewall of the first electrode, and an insulating layer disposed between the first electrode and the second electrode. The plurality of pads are disposed on the interconnect structure and electrically connected to the interconnect structure, wherein at least one of the plurality of pads is electrically connected to the capacitor.Type: ApplicationFiled: May 19, 2020Publication date: October 14, 2021Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Hsiao-Pei Lin, Shih-Ping Lee, Cheng-Zuo Han
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Publication number: 20210043633Abstract: Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer, and a capacitor. The first transistor and the second transistor are disposed on a substrate. Each of the first and second transistors includes a gate disposed on the substrate and two source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and the second transistors. The conductive layer is disposed above the first transistor and the second transistor, and includes a circuit portion, a first dummy portion, and a second dummy portion, wherein the circuit portion is electrically connected to the first transistor and the second transistor, the first dummy portion is located above the first transistor, and the second dummy portion is located above the second transistor. The capacitor is disposed on the substrate and located between the first dummy portion and the second dummy portion.Type: ApplicationFiled: October 21, 2020Publication date: February 11, 2021Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Shih-Ping Lee, Shyng-Yeuan Che, Hsiao-Pei Lin, Po-Yi Wu, Kuo-Fang Huang
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Publication number: 20210035980Abstract: Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer and a capacitor. Each of the first and second transistors includes a gate disposed on the substrate and source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The conductive layer is disposed above the first and second transistors and includes a circuit portion electrically connected to the first and second transistors and a dummy portion located above the isolation structure. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extension portions extend from the body portion to the source/drain regions of the first and the second transistors, respectively. The first and second extension portions are disposed between the circuit portion and the dummy portion, respectively.Type: ApplicationFiled: October 21, 2020Publication date: February 4, 2021Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Shih-Ping Lee, Shyng-Yeuan Che, Hsiao-Pei Lin, Po-Yi Wu, Kuo-Fang Huang
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Patent number: 10868017Abstract: Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer and a capacitor. Each of the first and second transistors includes a gate disposed on the substrate and source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The conductive layer is disposed above the first and second transistors and includes a circuit portion and a dummy portion. The circuit portion is electrically connected to the first and second transistors. The dummy portion is located above the isolation structure. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extension portions extend from the body portion to the source/drain regions of the first and the second transistors, respectively.Type: GrantFiled: March 19, 2019Date of Patent: December 15, 2020Assignee: Powerchip Semiconductor Manufacturing CorporationInventors: Shih-Ping Lee, Shyng-Yeuan Che, Hsiao-Pei Lin, Po-Yi Wu, Kuo-Fang Huang
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Publication number: 20200235102Abstract: Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer and a capacitor. The first and second transistors are disposed on the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The conductive layer is disposed above the first and second transistors and includes a circuit portion and a dummy portion. The circuit portion is electrically connected to the first and second transistors. The dummy portion is located above the isolation structure. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extension portions extend from the body portion to the source/drain regions of the first and the second transistors, respectively. The first and second extension portions are disposed between the circuit portion and the dummy portion, respectively.Type: ApplicationFiled: March 19, 2019Publication date: July 23, 2020Applicant: Powerchip Technology CorporationInventors: Shih-Ping Lee, Shyng-Yeuan Che, Hsiao-Pei Lin, Po-Yi Wu, Kuo-Fang Huang
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Patent number: 9842870Abstract: A bio-sensor includes a substrate having a light-sensing region thereon. A first dielectric layer, a diffusion barrier layer, and a second dielectric layer are disposed on the substrate. A trenched recess structure is formed in the second dielectric layer, which is filled with a light filter layer that is capped with a cap layer. A first passivation layer and a nanocavity construction layer are disposed on the cap layer. A nanocavity is formed in the nanocavity construction layer. The sidewall and bottom surface of the nanocavity is lined with a second passivation layer.Type: GrantFiled: June 3, 2017Date of Patent: December 12, 2017Assignee: Powerchip Technology CorporationInventors: Tse-Wei Chung, Tsung-Hui Chou, Che-Hung Lin, Shao-Wei Lu, Hsiao-Pei Lin
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Publication number: 20170271388Abstract: A bio-sensor includes a substrate having a light-sensing region thereon. A first dielectric layer, a diffusion barrier layer, and a second dielectric layer are disposed on the substrate. A trenched recess structure is formed in the second dielectric layer, which is filled with a light filter layer that is capped with a cap layer. A first passivation layer and a nanocavity construction layer are disposed on the cap layer. A nanocavity is formed in the nanocavity construction layer. The sidewall and bottom surface of the nanocavity is lined with a second passivation layer.Type: ApplicationFiled: June 3, 2017Publication date: September 21, 2017Inventors: Tse-Wei Chung, Tsung-Hui Chou, Che-Hung Lin, Shao-Wei Lu, Hsiao-Pei Lin
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Patent number: 9704898Abstract: A bio-sensor includes a substrate having a light-sensing region thereon. A first dielectric layer, a diffusion barrier layer, and a second dielectric layer are disposed on the substrate. A trenched recess structure is formed in the second dielectric layer, which is filled with a light filter layer that is capped with a cap layer. A first passivation layer and a nanocavity construction layer are disposed on the cap layer. A nanocavity is formed in the nanocavity construction layer. The sidewall and bottom surface of the nanocavity is lined with a second passivation layer.Type: GrantFiled: January 5, 2016Date of Patent: July 11, 2017Assignee: Powerchip Technology CorporationInventors: Tse-Wei Chung, Tsung-Hui Chou, Che-Hung Lin, Shao-Wei Lu, Hsiao-Pei Lin
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Publication number: 20170016830Abstract: A bio-sensor includes a substrate having a light-sensing region thereon. A first dielectric layer, a diffusion barrier layer, and a second dielectric layer are disposed on the substrate. A trenched recess structure is formed in the second dielectric layer, which is filled with a light filter layer that is capped with a cap layer. A first passivation layer and a nanocavity construction layer are disposed on the cap layer. A nanocavity is formed in the nanocavity construction layer. The sidewall and bottom surface of the nanocavity is lined with a second passivation layer.Type: ApplicationFiled: January 5, 2016Publication date: January 19, 2017Inventors: Tse-Wei Chung, Tsung-Hui Chou, Che-Hung Lin, Shao-Wei Lu, Hsiao-Pei Lin