Abstract: A method of generating optimized memory instances using a memory compiler is disclosed. Data pertinent to describing a memory to be designed are provided, and front-end models and back-end models are made to supply a library. Design criteria are received via a user interface. Design of the memory is optimized among speed, power and area according to the provided library and the received design criteria, thereby generating memory instances.

Abstract: A method of generating optimized memory instances using a memory compiler is disclosed. Data pertinent to describing a memory to be designed are provided, and front-end models and back-end models are made to supply a library. Design criteria are received via a user interface. Design of the memory is optimized among speed, power and area according to the provided library and the received design criteria, thereby generating memory instances.

Abstract: A thin film transistor substrate includes a transparent substrate, a plurality of thin film transistors, a passivation insulating layer and a plurality of pixel electrodes. The thin film transistors are disposed on the transparent substrate and include a gate insulating film. The passivation insulating layer is disposed on the gate insulating film and covers the thin film transistors, wherein the passivation insulating layer is formed with a concave-convex surface, a plurality of contact holes and a plurality of light-transmissive regions, and the light-transmissive regions are located above the gate insulating film. The pixel electrodes are disposed on the concave-convex surface and the light-transmissive regions, wherein each pixel electrode is electrically connected to the thin film transistor via the contact hole.

Abstract: A silicon chip having a mixed input/output slot structure comprising a core region having a plurality of circuits formed thereon, a wiring region surrounding and linked to the core region, and an input/output area surrounding and linked to the wiring region, where the input/output area has a plurality of input/output slots and four corner cells. The input/output slots can be divided into groups with each group having a different height, and input/output slots on the same side of the input/output area all have the same height. Therefore, a choice of sides for placing the input/output slots can be made, and the layout of input/output slots around the silicon chip is not be restricted by one side. Hence, chip size can be reduced and chip surface can be fully utilized.

Abstract: The invention provides an improvement in a cell structure for gate arrays. By using the cell in gate arrays, the design flexibility and the symmetry feature of the gate array can be retained. By providing transistors of different sizes, the design can possess more flexibility and more efficiency. Moreover, a denser chip layout can be completed. Thus, average wire lengths used for interconnections in the chip design may be shorter than previously possible. Also, better utilization of available chip area can be made. Thus, it becomes possible to flexibly and optimally use every area of the chip.