Patents by Inventor Hsiao-Ting Wu

Hsiao-Ting Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD OF MODIFYING POLYSILICON LAYER THROUGH NITROGEN INCORPORATION FOR ISOLATION STRUCTURE
    Publication number: 20150206789
    Abstract: The present disclosure relates to a method of modifying a polysilicon layer, which includes the following steps. A polysilicon layer is provided. Nitrogen is incorporated into the polysilicon layer toward a predetermined depth. The polysilicon layer incorporated with nitrogen is etched, wherein after the nitrogenized polysilicon is removed, the formation of the remaining polysilicon layer is nearly indistinguishable from the formation of the polysilicon layer.
    Type: Application
    Filed: January 17, 2014
    Publication date: July 23, 2015
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: JONATHAN PAPPAS, GIORGIO MARIOTTINI, DARWIN FAN, HSIAO TING WU, CHENG SHUN CHEN
  • Storage node of stack capacitor and fabrication method thereof
    Patent number: 7952127
    Abstract: A storage node structure includes a substrate having thereon a conductive block region; an etching stop layer covering the conductive block region; a conductive layer penetrating the etching stop layer and electrically connecting the conductive block region; an annular shaped conductive spacer on sidewall of the conductive layer, wherein the annular shaped conductive spacer is disposed on the etching stop layer and wherein the annular shaped conductive spacer and the conductive layer constitute a storage node pedestal; and an upper node portion stacked on the storage node pedestal.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: May 31, 2011
    Assignee: Nanya Technology Corp.
    Inventor: Hsiao-Ting Wu
  • STORAGE NODE OF STACK CAPACITOR AND FABRICATION METHOD THEREOF
    Publication number: 20100102374
    Abstract: A storage node structure includes a substrate having thereon a conductive block region; an etching stop layer covering the conductive block region; a conductive layer penetrating the etching stop layer and electrically connecting the conductive block region; an annular shaped conductive spacer on sidewall of the conductive layer, wherein the annular shaped conductive spacer is disposed on the etching stop layer and wherein the annular shaped conductive spacer and the conductive layer constitute a storage node pedestal; and an upper node portion stacked on the storage node pedestal.
    Type: Application
    Filed: December 31, 2008
    Publication date: April 29, 2010
    Inventor: Hsiao-Ting Wu