Abstract: An array substrate includes a scan line, a data line, a thin film transistor, a first transparent electrode, a passivation layer, and a second transparent electrode. The scan line and the data line interlace to define a pixel region. The gate dielectric layer of the thin film transistor overlaps the scan line and the data line and extends to cover the pixel region. The gate dielectric layer has a first region, a second region, and a third region. The first region corresponds to the semiconductor layer of the thin film transistor. The second region connects the first region and the third region. The thickness of the second region is different from that of the third region. The first transparent electrode covers the gate dielectric layer in the pixel region. The passivation layer covers the thin film transistor and the first transparent electrode. The second transparent electrode covers the passivation layer.

Abstract: A pixel structure includes a substrate, a plurality of gate lines and data lines, and at least one first pixel. The gate lines and the data lines are disposed on the substrate. The first pixel is disposed on the substrate and electrically connected to corresponding gate line and data line. The first pixel includes a first electrode, a first dielectric layer and a second electrode. The first electrode is disposed on the substrate. The first dielectric layer is disposed on the first electrode, and the first dielectric layer has at least one first island structure. The second electrode is disposed on a top surface of the first island structure, and the second electrode partially exposes the top surface of the first island structure.

Abstract: A display panel includes a first substrate, scan lines, data lines, pixel units, a second substrate, a display medium, and a color filter layer. The scan lines and the data lines are disposed on the first substrate. The pixel units are electrically connected to the scan lines and the data lines. Each pixel unit includes first, second, third, and fourth pixels. An extension direction of slit patterns of the first and second pixels is different from an extension direction of at least one of slit patterns of the third and fourth pixels. The color filter layer includes a first color filter pattern disposed corresponding to the first pixel, a second color filter pattern disposed corresponding to the second pixel, and a third color filter pattern disposed corresponding to the third pixel and the fourth pixel.

Abstract: A pixel structure includes a substrate, a plurality of gate lines and data lines, and at least one first pixel. The gate lines and the data lines are disposed on the substrate. The first pixel is disposed on the substrate and electrically connected to corresponding gate line and data line. The first pixel includes a first electrode, a first dielectric layer and a second electrode. The first electrode is disposed on the substrate. The first dielectric layer is disposed on the first electrode, and the first dielectric layer has at least one first island structure. The second electrode is disposed on a top surface of the first island structure, and the second electrode partially exposes the top surface of the first island structure.

Abstract: A display panel for a display device having a backlight module includes a first substrate, a plurality of data lines, a plurality of pixel electrodes, a dielectric layer, and a common electrode. The data lines are disposed substantially in parallel on the first substrate. The pixel electrodes are respectively disposed between the data lines. The dielectric layer covers the pixel electrodes and the data lines. The common electrode is disposed on the dielectric layer, and the common electrode has two first electrode branches, two second electrode branches, and two third electrode branches. The electrode branches are respectively and correspondingly disposed on the both sides of the pixel electrodes. The first electrode branches, the second electrode branches, and the third electrode branches respectively have a first interval, a second interval, and a third interval therebetween. The first interval is larger than the second interval and the third interval.

Abstract: A pixel structure including a scan line, a data line, an active device, a pixel electrode, a capacitor electrode line, a semi-conductive pattern layer and at least one dielectric layer is provided. The active device is electrically connected to the scan line and the data line. The pixel electrode is electrically connected to the active device. The capacitor electrode line is located under the pixel electrode. A first storage capacitor is formed between the capacitor electrode line and the pixel electrode. The semi-conductive pattern layer is disposed between the capacitor electrode line and the pixel electrode, the pixel electrode is electrically connected to the semi-conductive pattern layer. A second storage capacitor is formed between the semi-conductive pattern layer and the capacitor electrode line. The dielectric layer is disposed between the capacitor electrode line and the pixel electrode and located between the semi-conductive pattern layer and the capacitor electrode line.

Abstract: A pixel structure disposed on a first substrate is provided. The pixel structure includes a scan line, a data line, an active component, a pixel electrode, a first dielectric layer, a common electrode, and a protrusion. The scan line and the data line are disposed on the first substrate. The pixel electrode is disposed on the first substrate. The first dielectric layer is disposed on the first substrate and covers the pixel electrode. The common electrode is disposed on the first dielectric layer, and the common electrode has at least two first branched electrodes and a first opening between the first branched electrodes. The first branched electrodes and the first opening on the first substrate overlap with the pixel electrode in a projection direction. The protrusion is disposed on the first dielectric layer, and the protrusion is disposed in the first opening between the first branched electrodes.

Abstract: A pixel structure including a scan line, a data line, an active device, a pixel electrode, a capacitor electrode line, a semi-conductive pattern layer and at least one dielectric layer is provided. The active device is electrically connected to the scan line and the data line. The pixel electrode is electrically connected to the active device. The capacitor electrode line is located under the pixel electrode. A first storage capacitor is formed between the capacitor electrode line and the pixel electrode. The semi-conductive pattern layer is disposed between the capacitor electrode line and the pixel electrode, the pixel electrode is electrically connected to the semi-conductive pattern layer. A second storage capacitor is formed between the semi-conductive pattern layer and the capacitor electrode line. The dielectric layer is disposed between the capacitor electrode line and the pixel electrode and located between the semi-conductive pattern layer and the capacitor electrode line.

Abstract: A pixel unit includes a first pixel, a second pixel, a third pixel, a fourth pixel and a light-shielding structure. The first pixel has a plurality of first sub-pixels, the second pixel has a plurality of second sub-pixels, the third pixel has a plurality of third pixels, and the fourth pixel has a plurality of fourth sub-pixels. The first sub-pixel has a first electrode extending along a first tilting direction. The second sub-pixel has a second electrode extending along a second tilting direction. The third sub-pixel has a third electrode extending along a third tilting direction. The fourth sub-pixel has a fourth electrode extending along a fourth tilting direction. The first pixel, the second pixel, the third pixel and the fourth pixel surround the light-shielding structure collectively. The first tilting direction, the second tilting direction, the third tilting direction and the fourth tilting direction are different from each other.

Abstract: A liquid crystal display panel including a first substrate, scan lines extending along a first direction, data lines, active devices, pixel electrodes, common electrodes, a second substrate and a liquid crystal layer is provided. The pixel electrodes are respectively disposed in sub-pixel regions and coupled to the corresponding active devices. The common electrodes are respectively disposed corresponding to the pixel electrodes. Each common electrode or each pixel electrode includes plural stripe electrodes arranged side by side. Each stripe electrode includes a first section and a second section respectively disposed on two opposite sides of a reference axis, wherein a major axis of the first section forms an included angle with a major axis of the second section. The included angles of the stripe electrodes in each sub-pixel region are gradually varied along the first direction. The liquid crystal layer is disposed between the first substrate and the second substrate.

Abstract: A pixel structure includes a substrate, a scan line on the substrate, a data line set, an active device, and a pixel electrode. The substrate has a display region and a peripheral region around the display region. The display region includes at least one sub-pixel region. The data line set is disposed on the substrate, located at one side of the sub-pixel region, and intersected with the scan line to form at least one first intersecting region. The data line set includes a first and a second data lines that are intersected to form at least one second intersecting region. The first and the second data lines are electrically insulated. The active device electrically connects the scan line and to the first data line or the second data line in the data line set. The pixel electrode is located in the sub-pixel region and electrically connects the active device.

Abstract: A pixel structure including a scan line, a data line, an active device, a pixel electrode, a capacitor electrode line, a semi-conductive pattern layer and at least one dielectric layer is provided. The active device is electrically connected to the scan line and the data line. The pixel electrode is electrically connected to the active device. The capacitor electrode line is located under the pixel electrode. A first storage capacitor is formed between the capacitor electrode line and the pixel electrode. The semi-conductive pattern layer is disposed between the capacitor electrode line and the pixel electrode, the pixel electrode is electrically connected to the semi-conductive pattern layer. A second storage capacitor is formed between the semi-conductive pattern layer and the capacitor electrode line. The dielectric layer is disposed between the capacitor electrode line and the pixel electrode and located between the semi-conductive pattern layer and the capacitor electrode line.

Abstract: A pixel structure including a scan line, a data line, an active device, a pixel electrode, a capacitor electrode line, a semi-conductive pattern layer and at least one dielectric layer is provided. The active device is electrically connected to the scan line and the data line. The pixel electrode is electrically connected to the active device. The capacitor electrode line is located under the pixel electrode. A first storage capacitor is formed between the capacitor electrode line and the pixel electrode. The semi-conductive pattern layer is disposed between the capacitor electrode line and the pixel electrode, the pixel electrode is electrically connected to the semi-conductive pattern layer. A second storage capacitor is formed between the semi-conductive pattern layer and the capacitor electrode line. The dielectric layer is disposed between the capacitor electrode line and the pixel electrode and located between the semi-conductive pattern layer and the capacitor electrode line.

Abstract: A pixel structure including a scan line, a data line, an active device, a pixel electrode, a capacitor electrode line, a semi-conductive pattern layer and at least one dielectric layer is provided. The active device is electrically connected to the scan line and the data line. The pixel electrode is electrically connected to the active device. The capacitor electrode line is located under the pixel electrode. A first storage capacitor is formed between the capacitor electrode line and the pixel electrode. The semi-conductive pattern layer is disposed between the capacitor electrode line and the pixel electrode, the pixel electrode is electrically connected to the semi-conductive pattern layer. A second storage capacitor is formed between the semi-conductive pattern layer and the capacitor electrode line. The dielectric layer is disposed between the capacitor electrode line and the pixel electrode and located between the semi-conductive pattern layer and the capacitor electrode line.

Abstract: A Fringe-Field Switching (FFS) mode liquid crystal display (LCD) panel with optimized designs of pixel areas and/or liquid crystal materials is provided. The FFS mode LCD panel includes an active-element array substrate with a plurality of pixel areas, an opposite substrate, and a liquid crystal layer. Each pixel area comprises a plurality of first common electrodes, a second common electrode between the pixel area and another horizontally adjacent pixel area, and a pixel electrode. The optical transmittance and homogeneity of the pixel area of the display panel are modified by manipulating the relative position of the electrodes in the pixel areas on the active-element array substrate and/or adopting specific parameters of liquid crystal materials in the liquid crystal layer of the display panel.

Abstract: A display panel includes a first substrate, scan lines, data lines, pixel units, a second substrate, a display medium, and a color filter layer. The scan lines and the data lines are disposed on the first substrate. The pixel units are electrically connected to the scan lines and the data lines. Each pixel unit includes first, second, third, and fourth pixels. An extension direction of slit patterns of the first and second pixels is different from an extension direction of slit patterns of the third and fourth pixels. The color filter layer includes a first color filter pattern, a second color filter pattern, a third color filter pattern, and a fourth color filter pattern respectively corresponding to the first, second, third, and fourth pixel. The color of the fourth color filter pattern is different from the colors of the first, second, and third color filter patterns.

Abstract: A liquid crystal display panel including a first substrate, scan lines extending along a first direction, data lines, active devices, pixel electrodes, common electrodes, a second substrate and a liquid crystal layer is provided. The pixel electrodes are respectively disposed in sub-pixel regions and coupled to the corresponding active devices. The common electrodes are respectively disposed corresponding to the pixel electrodes. Each common electrode or each pixel electrode includes plural stripe electrodes arranged side by side. Each stripe electrode includes a first section and a second section respectively disposed on two opposite sides of a reference axis, wherein a major axis of the first section forms an included angle with a major axis of the second section. The included angles of the stripe electrodes in each sub-pixel region are gradually varied along the first direction. The liquid crystal layer is disposed between the first substrate and the second substrate.

Abstract: A display panel includes a first substrate, scan lines, data lines, pixel units, a second substrate, a display medium, and a color filter layer. The scan lines and the data lines are disposed on the first substrate. The pixel units are electrically connected to the scan lines and the data lines. Each pixel unit includes first, second, third, and fourth pixels. An extension direction of slit patterns of the first and second pixels is different from an extension direction of at least one of slit patterns of the third and fourth pixels. The color filter layer includes a first color filter pattern disposed corresponding to the first pixel, a second color filter pattern disposed corresponding to the second pixel, and a third color filter pattern disposed corresponding to the third pixel and the fourth pixel.

Abstract: A display panel includes a first substrate, scan lines, data lines, pixel units, a second substrate, a display medium, and a color filter layer. The scan lines and the data lines are disposed on the first substrate. The pixel units are electrically connected to the scan lines and the data lines. Each pixel unit includes first, second, third, and fourth pixels. An extension direction of slit patterns of the first and second pixels is different from an extension direction of slit patterns of the third and fourth pixels. The color filter layer includes a first color filter pattern, a second color filter pattern, a third color filter pattern, and a fourth color filter pattern respectively corresponding to the first, second, third, and fourth pixel. The color of the fourth color filter pattern is different from the colors of the first, second, and third color filter patterns.

Abstract: A pixel structure including a scan line, a data line, an active device, a pixel electrode, a capacitor electrode line, a semi-conductive pattern layer and at least one dielectric layer is provided. The active device is electrically connected to the scan line and the data line. The pixel electrode is electrically connected to the active device. The capacitor electrode line is located under the pixel electrode. A first storage capacitor is formed between the capacitor electrode line and the pixel electrode. The semi-conductive pattern layer is disposed between the capacitor electrode line and the pixel electrode, the pixel electrode is electrically connected to the semi-conductive pattern layer. A second storage capacitor is formed between the semi-conductive pattern layer and the capacitor electrode line. The dielectric layer is disposed between the capacitor electrode line and the pixel electrode and located between the semi-conductive pattern layer and the capacitor electrode line.