Patents by Inventor Hsiao-Wei Tsai

Hsiao-Wei Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8093653
    Abstract: A fabrication method of a trench metal oxide-semiconductor (MOS) transistor is provided. After the gate trenches are formed in the epitaxial layer, impurities of a first conductive type are implanted into the epitaxial layer by using a blanket implantation process. A polysilicon pattern filling the gate trenches and covering a predetermined range of epitaxial layer surrounding the gate trenches is formed on the epitaxial layer. Impurities of a second conductive type are implanted through the polysilicon pattern into the epitaxial layer to form a well. Impurities of the first conductive type are implanted to form a plurality of first doping regions. A portion of the polysilicon layer above the upper surface of the epitaxial layer is removed by etching to form a plurality of polysilicon gates. Impurities in the first doping regions are driven in to form a plurality of source regions adjacent to the gate trenches.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: January 10, 2012
    Assignee: Niko Semiconductor Co., Ltd.
    Inventors: Kao-Way Tu, Cheng-Hui Tung, Hsiao-Wei Tsai
  • Publication number: 20100078714
    Abstract: A fabrication method of a trench metal oxide-semiconductor (MOS) transistor is provided. After the gate trenches are formed in the epitaxial layer, impurities of a first conductive type are implanted into the epitaxial layer by using a blanket implantation process. A polysilicon pattern filling the gate trenches and covering a predetermined range of epitaxial layer surrounding the gate trenches is formed on the epitaxial layer. Impurities of a second conductive type are implanted through the polysilicon pattern into the epitaxial layer to form a well. Impurities of the first conductive type are implanted to form a plurality of first doping regions. A portion of the polysilicon layer above the upper surface of the epitaxial layer is removed by etching to form a plurality of polysilicon gates. Impurities in the first doping regions are driven in to form a plurality of source regions adjacent to the gate trenches.
    Type: Application
    Filed: October 1, 2008
    Publication date: April 1, 2010
    Applicant: NIKO SEMICONDUCTOR CO., LTD.
    Inventors: KAO-WAY TU, CHENG-HUI TUNG, HSIAO-WEI TSAI
  • Publication number: 20040082078
    Abstract: A test pen includes an integral hollow pen barrel. The hollow pen barrel is divided into four sections in order being a dip section, a testing and observation section, a drying section, and a sealed rear section. The dip section has a front opening allowing a slender water-absorbing member to pass therethrough. An air balance hole is provided on the dip section of the pen barrel to facilitate liquid siphoning. A pen cap for capping the dip section has a flexible inner fringe for keeping the dip section airtight. A rear plug is provided for sealing the rear section. A testing member is installed in the testing and observation section. The testing member includes a support card, a solid carrier, a conjugate release pad partially overlapping the front end of the solid carrier, an absorbing pad partially overlapping the rear end of the solid carrier, and a cover tape.
    Type: Application
    Filed: April 22, 2003
    Publication date: April 29, 2004
    Inventors: Hsiu-Hua Lin, Hsiao-Wei Tsai, Chih-Ming Lo