Patents by Inventor Hsiao-wen Liu

Hsiao-wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11963969
    Abstract: Provided is a pharmaceutical composition including gastrodin and a use thereof for the prevention or the treatment of amyotrophic lateral sclerosis. The pharmaceutical composition is effective in reducing neuronal axon degeneration and neurofibromin accumulation, improving symptoms of amyotrophic lateral sclerosis and extending life of patients of amyotrophic lateral sclerosis.
    Type: Grant
    Filed: September 16, 2022
    Date of Patent: April 23, 2024
    Assignee: BUDDHIST TZU CHI MEDICAL FOUNDATION
    Inventors: Chia-Yu Chang, Shinn-Zong Lin, Hsiao-Chien Ting, Hui-I Yang, Horng-Jyh Harn, Hong-Lin Su, Ching-Ann Liu, Yu-Shuan Chen, Tzyy-Wen Chiou, Tsung-Jung Ho
  • Patent number: 9245996
    Abstract: A LDMOS transistor device includes a substrate including a first insulating structure formed therein, a gate formed on the substrate and covering a portion of the first insulating structure, a drain region and a source region formed in the substrate at two respective sides of the gate, a base region encompassing the source region, and a doped layer formed under the base region. The drain region and the source region include a first conductivity type, the base region and the doped layer include a second conductivity type, and the second conductivity type is complementary to the first conductivity type. A top of the doped layer contacts a bottom of the base region. A width of the doped layer is larger than a width of the base region.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: January 26, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: An-Hung Lin, Bo-Jui Huang, Kun-Yi Chou, Hsiao-Wen Liu, Kai-Cheng Chang
  • Patent number: 9153454
    Abstract: A method of fabricating a high voltage device includes the step of forming a patterned photoresist layer on a conductive layer and a dielectric below the conductive. The conductive layer and the dielectric layer are patterned by taking the patterned photoresist layer as a mask. Subsequently the patterned photoresist layer is shrunk. The conductive layer and the dielectric layer are then patterned by taking the shrunk photoresist layer as a mask.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: October 6, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Hao Chen, Wen-Yu Lee, Hsiao-Wen Liu, Jung-Ching Chen
  • Publication number: 20150187933
    Abstract: A LDMOS transistor device includes a substrate including a first insulating structure formed therein, a gate formed on the substrate and covering a portion of the first insulating structure, a drain region and a source region formed in the substrate at two respective sides of the gate, a base region encompassing the source region, and a doped layer formed under the base region. The drain region and the source region include a first conductivity type, the base region and the doped layer include a second conductivity type, and the second conductivity type is complementary to the first conductivity type. A top of the doped layer contacts a bottom of the base region. A width of the doped layer is larger than a width of the base region.
    Type: Application
    Filed: January 2, 2014
    Publication date: July 2, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: An-Hung Lin, Bo-Jui Huang, Kun-Yi Chou, Hsiao-Wen Liu, Kai-Cheng Chang
  • Publication number: 20140370680
    Abstract: A method of fabricating a high voltage device includes the step of forming a patterned photoresist layer on a conductive layer and a dielectric below the conductive. The conductive layer and the dielectric layer are patterned by taking the patterned photoresist layer as a mask. Subsequently the patterned photoresist layer is shrunk. The conductive layer and the dielectric layer are then patterned by taking the shrunk photoresist layer as a mask.
    Type: Application
    Filed: June 17, 2013
    Publication date: December 18, 2014
    Inventors: Yi-Hao Chen, Wen-Yu Lee, Hsiao-Wen Liu, Jung-Ching Chen
  • Patent number: D661612
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: June 12, 2012
    Assignee: Hannstar Display Corporation
    Inventors: Shu-chen Hsu, Hsiao-wen Liu