Patents by Inventor Hsiao Yu Chia

Hsiao Yu Chia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10403743
    Abstract: A manufacturing method of an oxide semiconductor device includes the following steps. A first oxide semiconductor layer is formed on a substrate. A gate insulation layer is formed on the first oxide semiconductor layer. A first flattening process is performed on a top surface of the first oxide semiconductor layer before the step of forming the gate insulation layer. A roughness of the top surface of the first oxide semiconductor layer after the first flattening process is smaller than the roughness of the top surface of the first oxide semiconductor layer before the first flattening process.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: September 3, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Xiang Li, Shao-Hui Wu, Hsiao Yu Chia, Yu-Cheng Tung
  • Publication number: 20190109199
    Abstract: An oxide semiconductor device includes an oxide semiconductor channel layer, a first gate dielectric layer, a first gate electrode, a source electrode, and a drain electrode. The oxide semiconductor channel layer includes a channel region. The first gate dielectric layer is disposed on the oxide semiconductor channel layer. The first gate electrode is disposed on the first gate dielectric layer. The source electrode and the drain electrode are disposed at two opposite sides of the first gate electrode in a first direction respectively. The first gate electrode includes a metal material with a work function higher than 4.7 electron volts (eV). A thickness of the oxide semiconductor channel layer is smaller than one third of a length of the channel region in the first direction.
    Type: Application
    Filed: October 5, 2017
    Publication date: April 11, 2019
    Inventors: HAI BIAO YAO, Shao-Hui Wu, Xiang Li, HSIAO YU CHIA, Yu-Cheng Tung
  • Publication number: 20190081183
    Abstract: An oxide semiconductor device includes a substrate, a first patterned oxide semiconductor channel layer, a second oxide semiconductor channel layer, a gate dielectric layer, and a gate electrode. The first patterned oxide semiconductor channel layer is disposed on the substrate. The second patterned oxide semiconductor channel layer is disposed on the first patterned oxide semiconductor channel layer and covers a side edge of the first patterned oxide semiconductor channel layer. The gate dielectric layer is disposed on the second patterned oxide semiconductor channel layer. A top surface of the second patterned oxide semiconductor channel layer is fully covered by the gate dielectric layer. The gate electrode is disposed on the gate dielectric layer. A projection area of the gate electrode in a thickness direction of the substrate is smaller than a projection area of the second patterned oxide semiconductor channel layer in the thickness direction.
    Type: Application
    Filed: October 15, 2017
    Publication date: March 14, 2019
    Inventors: Xiang Li, Shao-Hui Wu, HSIAO YU CHIA, Yu-Cheng Tung
  • Publication number: 20190027589
    Abstract: A manufacturing method of an oxide semiconductor device includes the following steps. A first oxide semiconductor layer is formed on a substrate. A gate insulation layer is formed on the first oxide semiconductor layer. A first flattening process is performed on a top surface of the first oxide semiconductor layer before the step of forming the gate insulation layer. A roughness of the top surface of the first oxide semiconductor layer after the first flattening process is smaller than the roughness of the top surface of the first oxide semiconductor layer before the first flattening process.
    Type: Application
    Filed: July 20, 2017
    Publication date: January 24, 2019
    Inventors: Xiang Li, Shao-Hui Wu, HSIAO YU CHIA, Yu-Cheng Tung
  • Patent number: 10147614
    Abstract: A method of manufacturing an oxide semiconductor transistor is provided in the present invention, which includes the step of providing an oxide semiconductor transistor on the front side of a substrate, attaching a wafer on the front side of the substrate, forming a contact hole extending from the back side of the substrate to the oxide semiconductor layer of the oxide semiconductor transistor, and filling the contact hole with metal material to form a back gate of the oxide semiconductor transistor.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: December 4, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Xiang Li, Shao-Hui Wu, Hsiao Yu Chia, Yu-Cheng Tung