Abstract: A write-control circuit including a pulse processor and a waveform shifter is disclosed. The pulse processor is provided for processing a first waveform. When the first waveform has a bandwidth wider than a first delay, the waveform goes through the pulse processor without change. Otherwise, a second delay is added to trailing edge of the first waveform. The waveform shifter is provided for shifting the output waveform of the pulse processor as a second waveform. The pulse processor consists of a pulse generator, a trailing edge delay circuit, a NOR gate and an inverter. The pulse generator, which generates a finite-length pulse by the first waveform, includes a delay chain and a NAND gate. The delay chain may consist of an odd number of delay units. The trailing edge delay circuit includes an even number of delay units and a NAND gate for adding the second time delay to the trailing edge of the finite-length pulses.

Abstract: The present invention discloses an amendable static RAM, which can be modified from a high-priced corrupt 32K.times.36 one to a correctly functioning 32K.times.32 one. In each memory block, at least a common sense amplifier is employed as an amendable local sense amplifier. Each amendable local sense amplifier is coupled to a corresponding amendable common sense amplifier and by a switching circuit following the amendable common sense amplifier to all I/O buffers in the same memory block. When the static RAM works well and does not require amendment, the switching circuit is set to a normal condition that the amendable common sense amplifier is coupled to a corresponding amendable I/O buffers. When the static RAM is corrupt and requires modification, the switching circuit is set to an amendable condition wherein the amendable common sense amplifier is coupled to a normal I/O buffer corresponding to the corrupt memory column.

Abstract: An address buffer for high speed static random-access-memory (SRAM) devices is disclosed. The address buffer includes a buffer stage, an out-phase variable buffer circuit and an in-phase variable buffer circuit. The buffer stage includes a number of series-connected buffer units for transmitting an input address signal. The out-phase variable buffer circuit is connected to the buffer stage for providing a first buffer condition in a write period and for providing a second buffer condition in a read period. The in-phase variable buffer circuit is also connected to the buffer stage for providing a third buffer condition in the write period and for providing a fourth buffer condition in the read period. An external address signal can be delayed by the various buffer conditions of the address buffer during the write period to optimize the operation of the SRAM devices, and the various buffer conditions will not affect the read period.