Patents by Inventor Hsiao-Hui Wu

Hsiao-Hui Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Vertical gate field effect transistor
    Patent number: 11948949
    Abstract: In some embodiments, the present disclosure relates to a device having a semiconductor substrate including a frontside and a backside. On the frontside of the semiconductor substrate are a first source/drain region and a second source/drain region. A gate electrode is arranged on the frontside of the semiconductor substrate and includes a horizontal portion, a first vertical portion, and a second vertical portion. The horizontal portion is arranged over the frontside of the semiconductor substrate and between the first and second source/drain regions. The first vertical portion extends from the frontside towards the backside of the semiconductor substrate and contacts the horizontal portion of the gate electrode structure. The second vertical portion extends from the frontside towards the backside of the semiconductor substrate, contacts the horizontal portion of the gate electrode structure, and is separated from the first vertical portion by a channel region of the substrate.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Yuan Chen, Ching-Chun Wang, Hsiao-Hui Tseng, Jen-Cheng Liu, Jhy-Jyi Sze, Shyh-Fann Ting, Wei Chuang Wu, Yen-Ting Chiang, Chia Ching Liao, Yen-Yu Chen
  • Method and end cell library for avoiding substrate noise in an integrated circuit
    Patent number: 7409660
    Abstract: A method of avoiding substrate noise in an integrated circuit includes steps of receiving as input an integrated circuit design that includes at least a portion of a block for placement and routing on a substrate and an outer boundary of the block. An end cell is selected from a set of end cells for terminating the block in an outer area that extends from the outer boundary to an end cell boundary outside the block. The selected end cell is placed in the outer area to isolate the block electrically from the substrate.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: August 5, 2008
    Assignee: LSI Corporation
    Inventors: Chih-Ju Hung, Xiang Matthew Song, Hsiao-Hui Wu, Kai Lai, Fredrick Jen
  • Method and end cell library for avoiding substrate noise in an integrated circuit
    Publication number: 20070157145
    Abstract: A method of avoiding substrate noise in an integrated circuit includes steps of receiving as input from an integrated circuit design at least a portion of a block for placement and routing on a substrate and an outer boundary of the block, selecting an end cell from a set of end cells for terminating the block in an outer area that extends from the outer boundary to an end cell boundary outside the block, and placing the selected end cell in the outer area to isolate the block electrically from the substrate.
    Type: Application
    Filed: December 29, 2005
    Publication date: July 5, 2007
    Inventors: Chih-Ju Hung, Xiang Song, Hsiao-Hui Wu, Kai Lai, Fredrick Jen