Patents by Inventor Hsieh-Ching WEI

Hsieh-Ching WEI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of etching and cleaning wafers
    Patent number: 9583352
    Abstract: A method of operating a wafer processing system includes etching a batch of wafers. The method also includes transferring at least a portion of the batch of wafers to a first front opening universal pod (FOUP). The method further includes purging an interior of the first FOUP with an inert gas. The method additionally includes transporting the first FOUP from a first loading port to a second loading port. The method also includes monitoring an elapsed time from the purging. The method further includes performing a second purging of the interior of the first FOUP if the elapsed time exceeds a threshold time. The method additionally includes cleaning the batch of wafers.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: February 28, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Chang Tsai, Shao-Yen Ku, Hsieh-Ching Wei, Yuan Chih Chiang, Jui-Chuan Chang, Yung-Li Tsai
  • METHOD OF ETCHING AND CLEANING WAFERS
    Publication number: 20150357198
    Abstract: A method of operating a wafer processing system includes etching a batch of wafers. The method also includes transferring at least a portion of the batch of wafers to a first front opening universal pod (FOUP). The method further includes purging an interior of the first FOUP with an inert gas. The method additionally includes transporting the first FOUP from a first loading port to a second loading port. The method also includes monitoring an elapsed time from the purging. The method further includes performing a second purging of the interior of the first FOUP if the elapsed time exceeds a threshold time. The method additionally includes cleaning the batch of wafers.
    Type: Application
    Filed: August 18, 2015
    Publication date: December 10, 2015
    Inventors: Wen-Chang TSAI, Shao-Yen KU, Hsieh-Ching WEI, Yuan Chih CHIANG, Jui-Chuan CHANG, Yung-Li TSAI
  • Loading port, system for etching and cleaning wafers and method of use
    Patent number: 9136149
    Abstract: A loading port includes a housing and a plurality of stations defined in the housing configured to receive a front opening universal pod (FOUP). The loading port further includes a connector configured to receive an inert gas. At least one of the plurality of stations is configured to deliver the inert gas to the FOUP to purge an interior of the FOUP of moisture. A system including the loading port and a method of using the system are also described.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: September 15, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Chang Tsai, Shao-Yen Ku, Hsieh-Ching Wei, Yuan Chih Chiang, Jui-Chuan Chang, Yung-Li Tsai
  • LOADING PORT, SYSTEM FOR ETCHING AND CLEANING WAFERS AND METHOD OF USE
    Publication number: 20140141541
    Abstract: A loading port includes a housing and a plurality of stations defined in the housing configured to receive a front opening universal pod (FOUP). The loading port further includes a connector configured to receive an inert gas. At least one of the plurality of stations is configured to deliver the inert gas to the FOUP to purge an interior of the FOUP of moisture. A system including the loading port and a method of using the system are also described.
    Type: Application
    Filed: November 16, 2012
    Publication date: May 22, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Chang TSAI, Shao-Yen KU, Hsieh-Ching WEI, Yuan Chih CHIANG, Jui-Chuan CHANG, Yung-Li TSAI