Patents by Inventor Hsieh-Ming Chih

Hsieh-Ming Chih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus of addressing a memory integrated circuit
    Patent number: 8599640
    Abstract: A memory integrated circuit has control circuitry that accesses memory cells of the memory integrated circuit. The control circuitry is responsive to commands including a first command and a second command. The first command specifies a high order set of address bits. The second command specifies a low order set of address bits. The high order set of address bits and the low order set of address bits constitute a complete access address of the memory integrated circuit. The first command and the second command have different in command codes.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: December 3, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Chun-Hsiung Hung, Kuen-Long Chang, Hsieh Ming Chih
  • Method and Apparatus of Addressing A Memory Integrated Circuit
    Publication number: 20130094319
    Abstract: A memory integrated circuit has control circuitry that accesses memory cells of the memory integrated circuit. The control circuitry is responsive to commands including a first command and a second command. The first command specifies a high order set of address bits. The second command specifies a low order set of address bits. The high order set of address bits and the low order set of address bits constitute a complete access address of the memory integrated circuit. The first command and the second command have different in command codes.
    Type: Application
    Filed: December 7, 2012
    Publication date: April 18, 2013
    Inventors: Chun-Hsiung Hung, Kuen-Long Chang, Hsieh Ming Chih
  • Apparatus and method to tolerate floating input pin for input buffer
    Patent number: 8400190
    Abstract: An integrated circuit device includes a pad adapted to receive a signal from an internal or external driver, and an input buffer circuit including an input terminal coupled to the pad. The input buffer circuit includes a pass transistor having a control terminal, a first conduction terminal connected to the pad, and a second conduction terminal connected to a first voltage. The input buffer circuit also includes a latch having a terminal electrically coupled to the control terminal of the pass transistor. The input buffer circuit further includes circuitry coupled to the latch, the circuitry including a feedback transistor having a control terminal electrically coupled to the pad, a first conduction terminal electrically coupled to a second voltage, and a second conduction terminal coupled to the latch.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: March 19, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Chun-Hsiung Hung, Kuen-Long Chang, Nai-Ping Kuo, Hsieh-Ming Chih
  • Method and apparatus of addressing a memory integrated circuit
    Patent number: 8345505
    Abstract: A memory integrated circuit has control circuitry that accesses memory cells of the memory integrated circuit. The control circuitry is responsive to commands including a first command and a second command. The first command specifies a high order set of address bits. The second command specifies a low order set of address bits. The high order set of address bits and the low order set of address bits constitute a complete access address of the memory integrated circuit. The first command and the second command have different in command codes.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: January 1, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Chun-Hsiung Hung, Kuen-Long Chang, Hsieh-Ming Chih
  • Method and Apparatus of Addressing A Memory Integrated Circuit
    Publication number: 20110128809
    Abstract: A memory integrated circuit has control circuitry that accesses memory cells of the memory integrated circuit. The control circuitry is responsive to commands including a first command and a second command. The first command specifies a high order set of address bits. The second command specifies a low order set of address bits. The high order set of address bits and the low order set of address bits constitute a complete access address of the memory integrated circuit. The first command and the second command have different in command codes.
    Type: Application
    Filed: April 28, 2010
    Publication date: June 2, 2011
    Applicant: Macronix International Co., Ltd.
    Inventors: Chun-Hsiung Hung, Kuen-Long Chang, Hsieh-Ming Chih
  • APPARATUS AND METHOD TO TOLERATE FLOATING INPUT PIN FOR INPUT BUFFER
    Publication number: 20110068837
    Abstract: An integrated circuit device includes a pad adapted to receive a signal from an internal or external driver, and an input buffer circuit including an input terminal coupled to the pad. The input buffer circuit includes a pass transistor having a control terminal, a first conduction terminal connected to the pad, and a second conduction terminal connected to a first voltage. The input buffer circuit also includes a latch having a terminal electrically coupled to the control terminal of the pass transistor. The input buffer circuit further includes circuitry coupled to the latch, the circuitry including a feedback transistor having a control terminal electrically coupled to the pad, a first conduction terminal electrically coupled to a second voltage, and a second conduction terminal coupled to the latch.
    Type: Application
    Filed: September 23, 2009
    Publication date: March 24, 2011
    Applicant: Macronix International Co., Ltd.
    Inventors: CHUN-HSIUNG HUNG, Kuen-Long Chang, Nai-Ping Kuo, Hsieh-Ming Chih