Patents by Inventor Hsien-Chieh Tseng

Hsien-Chieh Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7842954
    Abstract: An active matrix array structure, disposed on a substrate, includes a first patterned conductive layer, a patterned gate insulating layer, a patterned semiconductor layer, a second patterned conductive layer, a patterned overcoat layer and a transparent conductive layer. The patterned gate insulating layer has first openings that expose a part of the first patterned conductive layer. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The second patterned conductive layer is disposed on the patterned semiconductor layer. The patterned overcoat layer has second openings that expose a part of the first patterned conductive layer and a part of the second patterned conductive layer. The transparent conductive layer is completely disposed on the substrate. The transparent conductive layer disposed in the first openings and the second openings is broken off at a position that is in between the substrate and the patterned overcoat layer.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: November 30, 2010
    Assignee: Au Optronics Corporation
    Inventors: Wei-Sheng Yu, Kuo-Lung Fang, Hsiang-Lin Lin, Hsien-Chieh Tseng, Han-Tu Lin
  • Publication number: 20100213464
    Abstract: An active matrix array structure, disposed on a substrate, includes a first patterned conductive layer, a patterned gate insulating layer, a patterned semiconductor layer, a second patterned conductive layer, a patterned overcoat layer and a transparent conductive layer. The patterned gate insulating layer has first openings that expose a part of the first patterned conductive layer. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The second patterned conductive layer is disposed on the patterned semiconductor layer. The patterned overcoat layer has second openings that expose a part of the first patterned conductive layer and a part of the second patterned conductive layer. The transparent conductive layer is completely disposed on the substrate. The transparent conductive layer disposed in the first openings and the second openings is broken off at a position that is in between the substrate and the patterned overcoat layer.
    Type: Application
    Filed: May 7, 2010
    Publication date: August 26, 2010
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Wei-Sheng Yu, Kuo-Lung Fang, Hsiang-Lin Lin, Hsien-Chieh Tseng, Han-Tu Lin
  • Patent number: 7754547
    Abstract: An active matrix array structure, disposed on a substrate, includes a first patterned conductive layer, a patterned gate insulating layer, a patterned semiconductor layer, a second patterned conductive layer, a patterned overcoat layer and a transparent conductive layer. The patterned gate insulating layer has first openings that expose a part of the first patterned conductive layer. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The second patterned conductive layer is disposed on the patterned semiconductor layer. The patterned overcoat layer has second openings that expose a part of the first patterned conductive layer and a part of the second patterned conductive layer. The transparent conductive layer is completely disposed on the substrate. The transparent conductive layer disposed in the first openings and the second openings is broken off at a position that is in between the substrate and the patterned overcoat layer.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: July 13, 2010
    Assignee: Au Optronics Corporation
    Inventors: Wei-Sheng Yu, Kuo-Lung Fang, Hsiang-Lin Lin, Hsien-Chieh Tseng, Han-Tu Lin
  • Publication number: 20090173943
    Abstract: An active matrix array structure, disposed on a substrate, includes a first patterned conductive layer, a patterned gate insulating layer, a patterned semiconductor layer, a second patterned conductive layer, a patterned overcoat layer and a transparent conductive layer. The patterned gate insulating layer has first openings that expose a part of the first patterned conductive layer. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The second patterned conductive layer is disposed on the patterned semiconductor layer. The patterned overcoat layer has second openings that expose a part of the first patterned conductive layer and a part of the second patterned conductive layer. The transparent conductive layer is completely disposed on the substrate. The transparent conductive layer disposed in the first openings and the second openings is broken off at a position that is in between the substrate and the patterned overcoat layer.
    Type: Application
    Filed: April 14, 2008
    Publication date: July 9, 2009
    Applicant: Au Optronics Corporation
    Inventors: Wei-Sheng Yu, Kuo-Lung Fang, Hsiang-Lin Lin, Hsien-Chieh Tseng, Han-Tu Lin