Abstract: The present invention discloses an electrode structure capable of separately delivering gas and fluid which is applied to a passive fuel cell. The electrode structure includes an electrode portion and a water removal plate, and the electrode portion is adjacent to the water removal plate. The water removal plate includes a first surface, a second surface opposite to the first surface, a plurality of gas passages passing from the first surface to the second surface, and a plurality of liquid passages disposed on the first surface. The surfaces of the gas passages are treated with hydrophobic treatment, and the surfaces of the liquid passages are treated with hydrophilic treatment.

Abstract: A set of nano/micro structured objects capable of interlocking with each other comprises a first part and a second part. A plurality of protrusions arranged in a matrix are disposed on a surface of a base plate of the first part. A plurality of microcavities arranged in a matrix are formed on a corresponding surface of the second part. The cross-sectional areas of a portion of each of the protrusions and microcavities decrease toward the base plate. A plurality of nano-scaled needle-shaped objects are formed on an outer sidewall of each of the protrusions or on an inner sidewall of each of the microcavities. When the two parts are combined, each of the protrusions is inserted into one of the microcavities, and the needle object of the protrusion bunts an inner sidewall of the microcavity, or the needle object of the microcavities bunts an outer sidewall of the protrusion.

Abstract: The present invention discloses an electrode structure capable of separately delivering gas and fluid which is applied to a passive fuel cell. The electrode structure includes an electrode portion and a water removal plate, and the electrode portion is adjacent to the water removal plate. The water removal plate includes a first surface, a second surface opposite to the first surface, a plurality of gas passages passing from the first surface to the second surface, and a plurality of liquor passages disposed on the first surface. The surfaces of the gas passages are treated with hydrophobic treatment, and the surfaces of the liquor passages are treated with hydrophilic treatment.

Abstract: The epitaxial lateral overgrowth (ELOG) GaN obtains the dangling structure by using wet etching and the transferred substrate to separate from the GaN epitaxy layer by using stress concentration of thermal expansion coefficient of the transferred substrate. It is useful to separate of the GaN epitaxy layer and transferred substrate by using anneal of wafer bonding. The present invention is to provide high selective etching rate, no damage to epitaxial film, low cost, and feasibility for larger commercial sizes. The wet etching method can not damage the separated epitaxial substrate, thus the substrate can be reused. There are various choices of handling substrate for bonding, not limited by the epitaxial method. When the epitaxial film is applied in devices, the low defect density of the epitaxial film can enhance the lifetime and efficiency of the devices. The addition of this improved fabrication process does not require expensive equipment. Moreover, it will reduce the production cost.

Abstract: Present invention is a method for lifting off GaN pseudomask epitaxy layer using wafer bonding way, wherein GaN epitaxy is obtained by way of selective area growth on a seed and the growth is in a way of pseudomask growth over a substrate. Owing to the different thermal expansion coefficients of the substrate and the GaN seed, by way of annealing and wafer bonding, the GaN epitaxy layer and the epitaxy substrate can be separated, or the GaN epitaxy substrate can be transferred onto another substrate. Thereby, the epitaxy substrate separated is not spoiled during the transferring procedure and can be reused, which lowers the cost; and high-quality GaN epitaxy layer can be transferred to various kinds of substrates for various kinds of usage and for solving the problems of difficulties in the production or the utilization of the substrate (such as difficulties in the cutting, the conductivity, the heat-sinking, and so on.

Abstract: A method to fabricate a 1T-RAM device, comprising the following steps. A semiconductor substrate having an access transistor area and an exposed bottom plate within a capacitor area proximate the access transistor area is provided. A gate with an underlying gate dielectric layer within the access transistor area are formed. The gate and underlying gate dielectric layer having sidewall spacers formed over their respective exposed side walls. A top plate with an underlying capacitor layer over the bottom plate within the capacitor area are formed. The top plate and underlying capacitor layer having sidewall spacers formed over their respective exposed side walls. A patterned resist protect oxide (RPO) layer is formed over at least the drain of the structure not to be silicided. Metal silicide portions are formed over the structure not protected by the RPO layer.

Abstract: A method to fabricate a 1T-RAM device, comprising the following steps. A semiconductor substrate having an access transistor area and an exposed bottom plate within a capacitor area proximate the access transistor area is provided. A gate with an underlying gate dielectric layer within the access transistor area are formed. The gate and underlying gate dielectric layer having sidewall spacers formed over their respective exposed side walls. A top plate with an underlying capacitor layer over the bottom plate within the capacitor area are formed. The top plate and underlying capacitor layer having sidewall spacers formed over their respective exposed side walls. A patterned resist protect oxide (RPO) layer is formed over at least the drain of the structure not to be silicided. Metal silicide portions are formed over the structure not protected by the RPO layer.

Abstract: A method to fabricate a 1T-RAM device, comprising the following steps. A semiconductor substrate having an access transistor area and an exposed bottom plate within a capacitor area proximate the access transistor area is provided. A gate with an underlying gate dielectric layer within the access transistor area are formed. The gate and underlying gate dielectric layer having sidewall spacers formed over their respective exposed side walls. A top plate with an underlying capacitor layer over the bottom plate within the capacitor area are formed. The top plate and underlying capacitor layer having sidewall spacers formed over their respective exposed side walls. A patterned resist protect oxide (RPO) layer is formed over at least the drain of the structure not to be silicided. Metal silicide portions are formed over the structure not protected by the RPO layer.