Patents by Inventor Hsien-Fu HSIAO
Hsien-Fu HSIAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10096583Abstract: The present invention relates to a compound semiconductor integrated circuit chip having a front and/or back surface metal layer used for electrical connection to an external circuit. The compound semiconductor integrated circuit chip (first chip) comprises a substrate, an electronic device layer, and a dielectric layer. A first metal layer is formed on the front side of the dielectric layer, and a third metal layer is formed on the back side of the substrate. The first and third metal layer are made essentially of Cu and used for the connection to other electronic circuits. A second chip may be mounted on the first chip with electrical connection made with the first or the third metal layer that extends over the electronic device in the first chip in the three-dimensional manner to make the electrical connection between the two chips having connection nodes away from each other.Type: GrantFiled: December 6, 2016Date of Patent: October 9, 2018Assignee: WIN Semiconductos Corp.Inventors: Shinichiro Takatani, Hsien-Fu Hsiao, Cheng-Kuo Lin, Chang-Hwang Hua
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Patent number: 9673186Abstract: The present invention relates to a compound semiconductor integrated circuit chip having a front and/or back surface metal layer used for electrical connection to an external circuit. The compound semiconductor integrated circuit chip (first chip) comprises a substrate, an electronic device layer, and a dielectric layer. A first metal layer is formed on the front side of the dielectric layer, and a third metal layer is formed on the back side of the substrate. The first and third metal layer are made essentially of Cu and used for the connection to other electronic circuits. A second chip may be mounted on the first chip with electrical connection made with the first or the third metal layer that extends over the electronic device in the first chip in the three-dimensional manner to make the electrical connection between the two chips having connection nodes away from each other.Type: GrantFiled: March 31, 2015Date of Patent: June 6, 2017Assignee: WIN SEMICONDUCTORS CORP.Inventors: Shinichiro Takatani, Hsien-Fu Hsiao, Cheng-Kuo Lin, Chang-Hwang Hua
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Publication number: 20170084592Abstract: The present invention relates to a compound semiconductor integrated circuit chip having a front and/or back surface metal layer used for electrical connection to an external circuit. The compound semiconductor integrated circuit chip (first chip) comprises a substrate, an electronic device layer, and a dielectric layer. A first metal layer is formed on the front side of the dielectric layer, and a third metal layer is formed on the back side of the substrate. The first and third metal layer are made essentially of Cu and used for the connection to other electronic circuits. A second chip may be mounted on the first chip with electrical connection made with the first or the third metal layer that extends over the electronic device in the first chip in the three-dimensional manner to make the electrical connection between the two chips having connection nodes away from each other.Type: ApplicationFiled: December 6, 2016Publication date: March 23, 2017Inventors: Shinichiro TAKATANI, Hsien-Fu Hsiao, Cheng-Kuo LIN, Chang-Hwang HUA
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Publication number: 20150206870Abstract: The present invention relates to a compound semiconductor integrated circuit chip having a front and/or back surface metal layer used for electrical connection to an external circuit. The compound semiconductor integrated circuit chip (first chip) comprises a substrate, an electronic device layer, and a dielectric layer. A first metal layer is formed on the front side of the dielectric layer, and a third metal layer is formed on the back side of the substrate. The first and third metal layer are made essentially of Cu and used for the connection to other electronic circuits. A second chip may be mounted on the first chip with electrical connection made with the first or the third metal layer that extends over the electronic device in the first chip in the three-dimensional manner to make the electrical connection between the two chips having connection nodes away from each other.Type: ApplicationFiled: March 31, 2015Publication date: July 23, 2015Inventors: Shinichiro TAKATANI, Hsien-Fu HSIAO, Cheng-Kuo LIN, Chang-Hwang HUA
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Patent number: 9070685Abstract: A compound semiconductor integrated circuit is provided, comprising a substrate, at least one compound semiconductor electronic device, a first metal layer, a protection layer, a plurality of second metal layers, and at least one dielectric layer. The first metal layer contains Au but does not contain Cu, and is at least partly electrically connected to the compound semiconductor electronic device. The protection layer covers the compound semiconductor electronic device and at least part of the first metal layer. Each of the plurality of second metal layers contains at least a Cu layer, and at least one of the plurality of second metal layers is partly electrically connected to the first metal layer described above. The at least one dielectric layer separates each pair of adjacent second metal layers. The second metal layers are used to form passive electronic components.Type: GrantFiled: August 24, 2012Date of Patent: June 30, 2015Assignee: WIN SEMICONDUCTORS CORP.Inventors: Shinichiro Takatani, Hsien-Fu Hsiao, Yu-Kai Wu
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Publication number: 20140209926Abstract: A compound semiconductor integrated circuit chip has a front and/or back surface metal layer used for electrical connection to an external circuit. The compound semiconductor integrated circuit chip (first chip) comprises a substrate, an electronic device layer, and a dielectric layer. A first metal layer is formed on the front side of the dielectric layer, and a third metal layer is formed on the back side of the substrate. The first and third metal layer are made essentially of Cu and used for the connection to other electronic circuits. A second chip may be mounted on the first chip with electrical connection made with the first or the third metal layer that extend over the electronic device in the first chip in the three-dimensional manner to make the electrical connection between the two chips having connection nodes away from each other.Type: ApplicationFiled: January 28, 2013Publication date: July 31, 2014Applicant: WIN SEMICONDUCTORS CORP.Inventors: Shinichiro TAKATANI, Hsien-Fu HSIAO, Cheng-Kuo LIN, Chang-Hwang HUA
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Publication number: 20140054608Abstract: A compound semiconductor integrated circuit is provided, comprising a substrate, at least one compound semiconductor electronic device, a first metal layer, a protection layer, a plurality of second metal layers, and at least one dielectric layer. The first metal layer contains Au but does not contain Cu, and is at least partly electrically connected to the compound semiconductor electronic device. The protection layer covers the compound semiconductor electronic device and at least part of the first metal layer. Each of the plurality of second metal layers contains at least a Cu layer, and at least one of the plurality of second metal layers is partly electrically connected to the first metal layer described above. The at least one dielectric layer separates each pair of adjacent second metal layers. The second metal layers are used to form passive electronic components.Type: ApplicationFiled: August 24, 2012Publication date: February 27, 2014Applicant: WIN SEMICONDUCTORS CORP.Inventors: Shinichiro TAKATANI, Hsien-Fu HSIAO, Yu-Kai WU