Patents by Inventor Hsien-Fu HSIAO
Hsien-Fu HSIAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240094145Abstract: A method and system for detecting the location of a surface defect on a transparent film with respect to whether the surface defect is at a front or back surface of the film. By illuminating the surface defect with a light source from an oblique angle and capturing an image of the surface defect using a camera which is positioned along an axis where the light illuminates after unobstructedly reflected from the test surface of the film, and using the reflected light, an image of the surface defect is obtained. A computer executes an evaluation logic to determine whether the image of the defect contains any dark area. If there is a dark area present, the defect is judged to be on the front surface of the film. If there is no dark area present, the defect is judged to be on the back surface of the film.Type: ApplicationFiled: March 27, 2023Publication date: March 21, 2024Inventors: Hsien-Te HSIAO, Hsuan-Fu WANG
-
Publication number: 20240077425Abstract: A detection method and system for inspecting a defect on a semi-reflective film by way of different light sources illuminated on the semi-reflective film along the same axis. More specifically, a P-polarized light source and an S-polarized light source are used to illuminate the defect on the semi-reflective film, with an illumination direction that is between 5-45 degrees relative to the semi-reflective film. A camera module captures an image to be inspected through the phenomenon that the P-polarized light will partially pass through the semi-reflective film, and the S-polarized light will be almost completely reflected by the semi-reflective film. During the detection, the defect is determined to be located on the front surface of the semi-reflective film when the S-polarized light is present in the image, and the defect is determined to be located on the back surface of the semi-reflective film when the P-polarized light is present in the image and no S-polarized light has entered the camera module.Type: ApplicationFiled: March 27, 2023Publication date: March 7, 2024Inventors: Hsien-Te HSIAO, Hsuan-Fu WANG
-
Patent number: 10096583Abstract: The present invention relates to a compound semiconductor integrated circuit chip having a front and/or back surface metal layer used for electrical connection to an external circuit. The compound semiconductor integrated circuit chip (first chip) comprises a substrate, an electronic device layer, and a dielectric layer. A first metal layer is formed on the front side of the dielectric layer, and a third metal layer is formed on the back side of the substrate. The first and third metal layer are made essentially of Cu and used for the connection to other electronic circuits. A second chip may be mounted on the first chip with electrical connection made with the first or the third metal layer that extends over the electronic device in the first chip in the three-dimensional manner to make the electrical connection between the two chips having connection nodes away from each other.Type: GrantFiled: December 6, 2016Date of Patent: October 9, 2018Assignee: WIN Semiconductos Corp.Inventors: Shinichiro Takatani, Hsien-Fu Hsiao, Cheng-Kuo Lin, Chang-Hwang Hua
-
Patent number: 9673186Abstract: The present invention relates to a compound semiconductor integrated circuit chip having a front and/or back surface metal layer used for electrical connection to an external circuit. The compound semiconductor integrated circuit chip (first chip) comprises a substrate, an electronic device layer, and a dielectric layer. A first metal layer is formed on the front side of the dielectric layer, and a third metal layer is formed on the back side of the substrate. The first and third metal layer are made essentially of Cu and used for the connection to other electronic circuits. A second chip may be mounted on the first chip with electrical connection made with the first or the third metal layer that extends over the electronic device in the first chip in the three-dimensional manner to make the electrical connection between the two chips having connection nodes away from each other.Type: GrantFiled: March 31, 2015Date of Patent: June 6, 2017Assignee: WIN SEMICONDUCTORS CORP.Inventors: Shinichiro Takatani, Hsien-Fu Hsiao, Cheng-Kuo Lin, Chang-Hwang Hua
-
Publication number: 20170084592Abstract: The present invention relates to a compound semiconductor integrated circuit chip having a front and/or back surface metal layer used for electrical connection to an external circuit. The compound semiconductor integrated circuit chip (first chip) comprises a substrate, an electronic device layer, and a dielectric layer. A first metal layer is formed on the front side of the dielectric layer, and a third metal layer is formed on the back side of the substrate. The first and third metal layer are made essentially of Cu and used for the connection to other electronic circuits. A second chip may be mounted on the first chip with electrical connection made with the first or the third metal layer that extends over the electronic device in the first chip in the three-dimensional manner to make the electrical connection between the two chips having connection nodes away from each other.Type: ApplicationFiled: December 6, 2016Publication date: March 23, 2017Inventors: Shinichiro TAKATANI, Hsien-Fu Hsiao, Cheng-Kuo LIN, Chang-Hwang HUA
-
Publication number: 20150206870Abstract: The present invention relates to a compound semiconductor integrated circuit chip having a front and/or back surface metal layer used for electrical connection to an external circuit. The compound semiconductor integrated circuit chip (first chip) comprises a substrate, an electronic device layer, and a dielectric layer. A first metal layer is formed on the front side of the dielectric layer, and a third metal layer is formed on the back side of the substrate. The first and third metal layer are made essentially of Cu and used for the connection to other electronic circuits. A second chip may be mounted on the first chip with electrical connection made with the first or the third metal layer that extends over the electronic device in the first chip in the three-dimensional manner to make the electrical connection between the two chips having connection nodes away from each other.Type: ApplicationFiled: March 31, 2015Publication date: July 23, 2015Inventors: Shinichiro TAKATANI, Hsien-Fu HSIAO, Cheng-Kuo LIN, Chang-Hwang HUA
-
Patent number: 9070685Abstract: A compound semiconductor integrated circuit is provided, comprising a substrate, at least one compound semiconductor electronic device, a first metal layer, a protection layer, a plurality of second metal layers, and at least one dielectric layer. The first metal layer contains Au but does not contain Cu, and is at least partly electrically connected to the compound semiconductor electronic device. The protection layer covers the compound semiconductor electronic device and at least part of the first metal layer. Each of the plurality of second metal layers contains at least a Cu layer, and at least one of the plurality of second metal layers is partly electrically connected to the first metal layer described above. The at least one dielectric layer separates each pair of adjacent second metal layers. The second metal layers are used to form passive electronic components.Type: GrantFiled: August 24, 2012Date of Patent: June 30, 2015Assignee: WIN SEMICONDUCTORS CORP.Inventors: Shinichiro Takatani, Hsien-Fu Hsiao, Yu-Kai Wu
-
Publication number: 20140209926Abstract: A compound semiconductor integrated circuit chip has a front and/or back surface metal layer used for electrical connection to an external circuit. The compound semiconductor integrated circuit chip (first chip) comprises a substrate, an electronic device layer, and a dielectric layer. A first metal layer is formed on the front side of the dielectric layer, and a third metal layer is formed on the back side of the substrate. The first and third metal layer are made essentially of Cu and used for the connection to other electronic circuits. A second chip may be mounted on the first chip with electrical connection made with the first or the third metal layer that extend over the electronic device in the first chip in the three-dimensional manner to make the electrical connection between the two chips having connection nodes away from each other.Type: ApplicationFiled: January 28, 2013Publication date: July 31, 2014Applicant: WIN SEMICONDUCTORS CORP.Inventors: Shinichiro TAKATANI, Hsien-Fu HSIAO, Cheng-Kuo LIN, Chang-Hwang HUA
-
Publication number: 20140054608Abstract: A compound semiconductor integrated circuit is provided, comprising a substrate, at least one compound semiconductor electronic device, a first metal layer, a protection layer, a plurality of second metal layers, and at least one dielectric layer. The first metal layer contains Au but does not contain Cu, and is at least partly electrically connected to the compound semiconductor electronic device. The protection layer covers the compound semiconductor electronic device and at least part of the first metal layer. Each of the plurality of second metal layers contains at least a Cu layer, and at least one of the plurality of second metal layers is partly electrically connected to the first metal layer described above. The at least one dielectric layer separates each pair of adjacent second metal layers. The second metal layers are used to form passive electronic components.Type: ApplicationFiled: August 24, 2012Publication date: February 27, 2014Applicant: WIN SEMICONDUCTORS CORP.Inventors: Shinichiro TAKATANI, Hsien-Fu HSIAO, Yu-Kai WU