Abstract: The fiber optic connector includes a connector head module, a mounting seat, a rear boot, an engaging module and a sheath member. The mounting seat is mounted to a rear end of the connector head module, and includes an external threaded portion. The rear boot is connected to a rear end of the mounting seat. The engaging module is removably coupled to the connector head module. The sheath member includes an internal threaded portion that is formed in an inner surface of the sheath member. When the engaging module is removed from the connector head module, the sheath member can be attachable to the mounting seat with the external threaded portion being threadedly engaged with the external threaded portion of the mounting seat.

Abstract: A fiber optic adapter includes a shielding casing that is connected to a casing body and that defines a through channel. Two engagement members extend from a casing body and extend through the through channel. A pivot shaft engages the shielding casing. A shielding plate is connected to the pivot shaft. A restoring member is sleeved on the pivot shaft. The shielding plate is pivotable about the pivot shaft against a resilient force of the restoring member from a shielding position to an open position relative to the shielding casing. When the shielding plate is in the shielding position, the shielding plate is disposed between the engagement members and shields the through channel. When the shielding plate is in the open position, the shielding plate opens the through channel.

Abstract: One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor.

Abstract: One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor.

Abstract: One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor.

Abstract: Among other things, one or more systems and techniques for width bias adjustment for a design layout are provided. During fabrication, characteristics of a component can change, such as size, width, position, etc., from how a design layout represents such components. Accordingly, a width bias table is used to identify a width bias value that can be applied between a first polygon and a second polygon to compensate for a characteristic change associated with at least one of the first polygon and the second polygon during fabrication. The width bias value is used during RC extraction to determine an electrical characteristic adjustment, such as an additional capacitance or resistance associated with the width bias value, for at least one of the first polygon and the second polygon. In this way, RC extraction, during a design phase, can take into account electrical characteristic changes that occur during fabrication.

Abstract: One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor.

Abstract: A computer system is disclosed. The computer system includes a higher level cache, a lower level cache, a decoder to decode instructions, and a circuit coupled to the decoder. In one embodiment, the circuit, in response to a single decoded instruction, retrieves data from external memory and bypasses the lower level cache upon a higher level cache miss. In another embodiment, the circuit, in response to a first decoded instruction, issues a request to retrieve data at an address from external memory to place said data only in the lower level cache, detects a second cacheable decoded instruction to said address, and places said data in the higher level cache.

Abstract: The present invention is directed to a method and apparatus for processing normalized meshes. The normalized meshes are formed by N polygons which have M vertices. M vertex coordinates are stored in a vertex array corresponding to the M vertices of the N polygons. N polygon indices are stored in an index array. Each of the N polygon indices references a predetermined number of the M vertex coordinates. A first subset of the index array having N1 polygon indices is determined. A second subset of the vertex array is selected such that the second subset contains M1 vertex coordinates corresponding entirely to the N1 polygon indices in the first subset. The second subset defines a window having a small size relative to the vertex array. The M1 vertex coordinates in the second subset are processed to generate processed data. The processed data are then concurrently sent to a graphics processor in an on-line manner.

Abstract: The present invention discloses a method and apparatus method for efficient utilization of write-combining buffers for a sequence of non-temporal stores to scattered locations. The method comprises: converting the sequence of non-temporal stores to stores to intermediate buffers; and grouping the stores to intermediate buffers into consecutive non-temporal stores. The consecutive non-temporal stores correspond to adjacent memory locations in the write-combining buffers.

Abstract: The present invention is directed to a method and apparatus for processing normalized meshes. The normalized meshes are formed by N polygons which have M vertices. M vertex coordinates are stored in a vertex array corresponding to the M vertices of the N polygons. N polygon indices are stored in an index array. Each of the N polygon indices references a predetermined number of the M vertex coordinates. A first subset of the index array having N1 polygon indices is determined. A second subset of the vertex array is selected such that the second subset contains M1 vertex coordinates corresponding entirely to the N1 polygon indices in the first subset. The second subset defines a window having a small size relative to the vertex array. The M1 vertex coordinates in the second subset are processed to generate processed data. The processed data are then concurrently sent to a graphics processor in an on-line manner.

Abstract: The present invention discloses a method and apparatus method for efficient utilization of write-combining buffers for a sequence of non-temporal stores to scattered locations. The method comprises: converting the sequence of non-temporal stores to stores to intermediate buffers; and grouping the stores to intermediate buffers into consecutive non-temporal stores. The consecutive non-temporal stores correspond to adjacent memory locations in the write-combining buffers.

Abstract: The present invention discloses a method and apparatus for processing strips of data, each strip referencing a plurality of parameter sets stored in a memory. The method comprises: prefetching a plurality of parameter sets referenced in a first strip; performing an operation on each of the prefetched parameter sets; and concatenating a first strip and a second strip to eliminate a memory access latency in the second strip.