Abstract: A semiconductor structure is provided. The semiconductor structure includes an insulator layer, first and second field-effect transistor devices, an isolation field-effect transistor device, front-side gate and back-side gate contacts. Each of the first and second field-effect transistor devices and the isolation field-effect transistor device includes a fin structure and first and second epitaxial source/drain structures. The fin structure includes channel layers and a gate structure that is wrapped around the channel layers. The first and second epitaxial source/drain structures are connected to opposite sides of the channel layers. The isolation field-effect transistor device is kept in the off-state. The front-side gate contact is formed on the first field-effect transistor device and electrically connected to the gate structure of the first field-effect transistor device.

Abstract: A semiconductor device and method for forming same. According to an embodiment. The method provides a base substrate, forms a heat dissipation substrate on the base substrate, wherein a thermal conductivity of the heat dissipation substrate is between 200 Wm?1K?1 and 1200 Wm?1K?1. This method further forms a device layer on the heat dissipation substrate, wherein the device layer comprises a transistor. The method further removes the base substrate.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a fin structure and an epitaxial source/drain structure. The substrate includes a substrate layer and an insulator layer on the substrate layer. The fin structure is formed over the substrate, wherein the fin structure includes a gate structure and channel layers wrapped by the gate structure. The epitaxial source/drain structure is connected to the channel layers, wherein a bottom portion of the epitaxial source/drain structure is in contact with the insulator layer of the substrate.

Abstract: A semiconductor structure is provided. The semiconductor structure includes an insulator layer, first and second field-effect transistor devices, an isolation field-effect transistor device, front-side gate and back-side gate contacts. Each of the first and second field-effect transistor devices and the isolation field-effect transistor device includes a fin structure and first and second epitaxial source/drain structures. The fin structure includes channel layers and a gate structure that is wrapped around the channel layers. The first and second epitaxial source/drain structures are connected to opposite sides of the channel layers. The isolation field-effect transistor device is kept in the off-state. The front-side gate contact is formed on the first field-effect transistor device and electrically connected to the gate structure of the first field-effect transistor device.

Abstract: A semiconductor device and method for forming same. According to an embodiment. The method provides a base substrate, forms a heat dissipation substrate on the base substrate, wherein a thermal conductivity of the heat dissipation substrate is between 200 Wm?1K?1and 1200 Wm?1K?1. This method further forms a device layer on the heat dissipation substrate, wherein the device layer comprises a transistor. The method further removes the base substrate.

Abstract: A semiconductor device includes a heat dissipation substrate and a device layer. The thermal conductivity of the heat dissipation substrate is greater than 200 Wm?1K?1 and the device layer is disposed on the heat dissipation substrate. The device layer includes a transistor. A method of forming a semiconductor device includes providing a base substrate, forming a heat dissipation substrate on the base substrate, wherein a thermal conductivity of the heat dissipation substrate is greater than 200 Wm?1K?1. The method further includes forming a device layer on the heat dissipation substrate, wherein the device layer comprises a transistor. The method further includes removing the base substrate.

Abstract: A method includes etching a trench in a substrate adjacent to a gate structure, wherein the trench includes a bottom surface and a tip portion extending under a spacer of the gate structure. The method further includes epitaxially growing a first semiconductor material in the trench, wherein the first semiconductor material covers an entirety of the bottom surface of the trench, and the first semiconductor material grows in the tip portion. The method further includes epitaxially growing a second semiconductor material in the trench, wherein the second semiconductor material is different from the first semiconductor material, the second semiconductor material covers the first semiconductor material, and the second semiconductor material directly contacts the substrate between the bottom surface of the trench and the tip portion.

Abstract: A device includes a substrate and a gate structure over the substrate. The device further includes source/drain (S/D) features in the substrate. At least one of the S/D features is located in a trench. The at least one S/D feature includes a first semiconductor material covering an entirety of a bottom surface of the trench. The at least one S/D feature further includes a second semiconductor material over the first semiconductor material. The at least one S/D feature further includes a third semiconductor material over the second semiconductor material. The second semiconductor material has a composition different from the first semiconductor material and the third semiconductor material. The first semiconductor material includes physically discontinuous portions directly contacting the substrate. The second semiconductor material surrounds the third semiconductor material.

Abstract: A semiconductor device includes a heat dissipation substrate and a device layer. The thermal conductivity of the heat dissipation substrate is greater than 200 Wm?1K?1and the device layer is disposed on the heat dissipation substrate. The device layer includes a transistor.

Abstract: A method for forming a self-aligned contact includes providing a substrate with a plurality of gate structures including spacers on opposite sides. The method also includes forming a sacrificial layer between the gate structures. The method also includes forming a mask layer on a part of the sacrificial layer. The method also includes forming a plurality of first openings by removing the sacrificial layer exposed from the mask layer. The method also includes forming a dielectric layer in the plurality of first openings. The method also includes removing the mask layer. The method also includes forming a plurality of second openings by removing the sacrificial layer that remains on the substrate. The method also includes forming a plurality of first contact plugs in the second openings.

Abstract: The invention provides a semiconductor device. The semiconductor device includes a gate structure over fin structures arranged in parallel. Each of the fin structures has a drain portion and a source portion on opposite sides of the gate structure. A drain contact structure is positioned over the drain portions of the fin structures. A source contact structure is positioned over the source portions of the fin structures. A first amount of drain via structures is electrically connected to the drain contact structure. A second amount of source via structures is electrically connected to the source contact structure. The sum of the first amount and the second amount is greater than or equal to 2, and the sum of the first amount and the second amount is less than or equal to two times the amount of fin structures.

Abstract: A method for forming a self-aligned contact includes providing a substrate with a plurality of gate structures including spacers on opposite sides. The method also includes forming a sacrificial layer between the gate structures. The method also includes forming a mask layer on a part of the sacrificial layer. The method also includes forming a plurality of first openings by removing the sacrificial layer exposed from the mask layer. The method also includes forming a dielectric layer in the plurality of first openings. The method also includes removing the mask layer. The method also includes forming a plurality of second openings by removing the sacrificial layer that remains on the substrate. The method also includes forming a plurality of first contact plugs in the second openings.

Abstract: A device includes a substrate and a gate structure over the substrate. The device further includes source/drain (S/D) features in the substrate. At least one of the S/D features is located in a trench. The at least one S/D feature includes a first semiconductor material covering an entirety of a bottom surface of the trench. The at least one S/D feature further includes a second semiconductor material over the first semiconductor material. The at least one S/D feature further includes a third semiconductor material over the second semiconductor material. The second semiconductor material has a composition different from the first semiconductor material and the third semiconductor material. The first semiconductor material includes physically discontinuous portions directly contacting the substrate. The second semiconductor material surrounds the third semiconductor material.

Abstract: The invention provides a semiconductor device. The semiconductor device includes a gate structure over fin structures arranged in parallel. Each of the fin structures has a drain portion and a source portion on opposite sides of the gate structure. A drain contact structure is positioned over the drain portions of the fin structures. A source contact structure is positioned over the source portions of the fin structures. A first amount of drain via structures is electrically connected to the drain contact structure. A second amount of source via structures is electrically connected to the source contact structure. The sum of the first amount and the second amount is greater than or equal to 2, and the sum of the first amount and the second amount is less than or equal to two times the amount of fin structures.

Abstract: A device includes a substrate, a gate structure over the substrate, and source/drain (S/D) features in the substrate and interposed by the gate structure. At least one of the S/D features includes a first semiconductor material, a second semiconductor material over the first semiconductor material, and a third semiconductor material over the second semiconductor material. The second semiconductor material has a composition different from the first semiconductor material and the third semiconductor material. The first semiconductor material includes physically discontinuous portions.

Abstract: In a method, a gate structure is formed over a substrate, and source/drain (S/D) features are formed in the substrate and interposed by the gate structure. At least one of the S/D features is formed by forming a first semiconductor material including physically discontinuous portions, forming a second semiconductor material over the first semiconductor material, and forming a third semiconductor material over the second semiconductor material. The second semiconductor material has a composition different from a composition of the first semiconductor material. The third semiconductor material has a composition different from the composition of the second semiconductor material.

Abstract: A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin.

Abstract: A method of fabricating an integrated circuit device includes forming a first gate structure in a first region of a substrate and a second gate structure in a second region of the substrate. The method includes forming a protective layer overlying the first and the second gate structures. The method includes removing a portion of the protective layer over the second gate structure. The method includes forming features adjacent to the second gate structure. The method further includes forming a spacer over at least a portion of the features adjacent to the second gate structure, wherein the features separate the spacer from the substrate adjacent to the second gate structure. The method includes removing the second portion of the protective layer. Removing the second portion of the protective layer includes forming a protector over the second gate structure; and performing an etching process using a chemical comprising hydrofluoric acid (HF).

Abstract: A system and method for forming semiconductor structures is disclosed. An embodiment comprises forming a high diffusibility layer adjacent to a gate stack and forming a low diffusibility layer adjacent to the high diffusibility layer. After these two layers are formed, an anneal is performed to diffuse dopants from the high diffusibility layer underneath the gate stack to help form a channel region.

Abstract: An integrated circuit structure includes a fin field-effect transistor (FinFET) including a semiconductor fin over and adjacent to insulation regions; and a source/drain region over the insulation regions. The source/drain region includes a first and a second semiconductor region. The first semiconductor region includes silicon and an element selected from the group consisting of germanium and carbon, wherein the element has a first atomic percentage in the first semiconductor region. The first semiconductor region has an up-slant facet and a down-slant facet. The second semiconductor region includes silicon and the element. The element has a second atomic percentage lower than the first atomic percentage. The second semiconductor region has a first portion on the up-slant facet and has a first thickness. A second portion of the second semiconductor region, if any, on the down-slant facet has a second thickness smaller than the first thickness.