Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.

Abstract: Provided are structures and methods for forming structures with sloping surfaces of a desired profile. An exemplary method includes performing a first etch process to differentially etch a gate material to a recessed surface, wherein the recessed surface includes a first horn at a first edge, a second horn at a second edge, and a valley located between the first horn and the second horn; depositing an etch-retarding layer over the recessed surface, wherein the etch-retarding layer has a central region over the valley and has edge regions over the horns, and wherein the central region of the etch-retarding layer is thicker than the edge regions of the etch-retarding layer; and performing a second etch process to recess the horns to establish the gate material with a desired profile.

Abstract: Methods for fabricating semiconductor structures are provided. An exemplary method includes forming a first transistor structure and a second transistor structure over a substrate, wherein each transistor structure includes at least one nanosheet. The method further includes depositing a metal over each transistor structure and around each nanosheet; depositing a coating over the metal; depositing a mask over the coating; and patterning the mask to define a patterned mask, wherein the patterned mask lies over a masked portion of the coating and the second transistor structure, and wherein the patterned mask does not lie over an unmasked portion of the coating and the first transistor structure. The method further includes etching the unmasked portion of the coating and the metal over the first transistor structure using a dry etching process with a process pressure of from 30 to 60 (mTorr).

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

Abstract: A write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.

Abstract: A method for fabricating semiconductor devices is disclosed. The method includes forming a gate trench over a semiconductor channel, the gate trench being surrounded by gate spacers. The method includes sequentially depositing a work function metal, a glue metal, and an electrode metal in the gate trench. The method includes etching respective portions of the electrode metal and the glue metal to form a gate electrode above a metal gate structure. The metal gate structure includes a remaining portion of the work function metal and the gate electrode includes a remaining portion of the electrode metal. The gate electrode has an upper surface extending away from a top surface of the metal gate structure.

Abstract: Disclosed is a semiconductor fabrication method. The method includes forming a gate stack in an area previously occupied by a dummy gate structure; forming a first metal cap layer over the gate stack; forming a first dielectric cap layer over the first metal cap layer; selectively removing a portion of the gate stack and the first metal cap layer while leaving a sidewall portion of the first metal cap layer that extends along a sidewall of the first dielectric cap layer; forming a second metal cap layer over the gate stack and the first metal cap layer wherein a sidewall portion of the second metal cap layer extends further along a sidewall of the first dielectric cap layer; forming a second dielectric cap layer over the second metal cap layer; and flattening a top layer of the first dielectric cap layer and the second dielectric cap layer using planarization operations.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor fin. The semiconductor device includes first spacers over the semiconductor fin. The semiconductor device includes a metal gate structure, over the semiconductor fin, that is sandwiched at least by the first spacers. The semiconductor device includes a gate electrode contacting the metal gate structure. An interface between the metal gate structure and the gate electrode has its side portions extending toward the semiconductor fin with a first distance and a central portion extending toward the semiconductor fin with a second distance, the first distance being substantially less than the second distance.

Abstract: A motor comprises a stator, heatsinks, a rotor and a heat-dissipation device. The stator has a hollow portion, a coil portion and a housing portion having a first surface, a second surface and sidewalls. The hollow portion is penetrated through the housing portion. The coil portion is disposed between the hollow portion and the housing portion. The heatsinks are respectively disposed on different sidewalls. The heat-dissipation device comprises a wind-guiding cover and a first fan. The wind-guiding cover comprises a wind-guiding main board and wind-guiding lateral boards. The wind-guiding main board is disposed adjacent to the second surface. The wind-guiding lateral boards are vertically extended from different lateral edges of the wind-guiding main board towards the same direction. Each wind-guiding lateral board is disposed corresponding to one of the heatsinks, and at least one of the wind-guiding lateral boards has a hole. The first fan is received by the hole.

Abstract: A motor comprises a stator, heatsinks, a rotor and a heat-dissipation device. The stator has a hollow potion, a coil portion and a housing portion having a first surface, a second surface and sidewalls. The hollow portion is penetrated through the housing portion. The coil portion is disposed between the hollow portion and the housing portion. The heatsinks are respectively disposed on different sidewalls. The heat-dissipation device comprises a wind-guiding cover and a first fan. The wind-guiding cover comprises a wind-guiding main board and wind-guiding lateral boards. The wind-guiding main board is disposed adjacent to the second surface. The wind-guiding lateral boards are vertically extended from different lateral edges of the wind-guiding main board towards the same direction. Each wind-guiding lateral board is disposed corresponding to one of the heatsinks, and at least one of the wind-guiding lateral boards has a hole. The first fan is received by the hole.

Abstract: A key apparatus includes a housing with an opening, a printed circuit board (PCB) received in the housing, and a key mechanism. The key mechanism includes an electrode portion and a conducting portion sandwiched between the electrode portion and the PCB. The electrode portion is electrically connected to the PCB. The conducting portion is apart from the PCB. While the conducting portion connects with the connecting region, the electrode portion and the connecting region form a capacitor. The PCB generates different control signals based on different capacitances of the formed capacitors.

Abstract: A key apparatus includes a housing with an opening, a printed circuit board (PCB) received in the housing, and a key mechanism. The key mechanism includes an electrode portion and a conducting portion sandwiched between the electrode portion and the PCB. The electrode portion is electrically connected to the PCB. The conducting portion is apart from the PCB. While the conducting portion connects with the connecting region, the electrode portion and the connecting region form a capacitor. The PCB generates different control signals based on different capacitances of the formed capacitors.

Abstract: A key apparatus includes a housing with an opening, a printed circuit board (PCB) received in the housing, and a key mechanism. The key mechanism includes at least one key and an elastic portion. The key and the elastic portion are partly exposed from the housing via the opening. The elastic portion deforms to generate an elastic force and the key remains in an original position. The elastic drives the key to move simultaneously for providing an elastic force. The key mechanism provides a two stage touch feeling to a user when being pressed.