Patents by Inventor Hsien-Jung Chen

Hsien-Jung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240332261
    Abstract: A method of manufacturing a die stack structure includes the following steps. A first bonding structure is formed over a front side of a first die. The method of forming the first bonding structure includes the following steps. A first bonding dielectric material is formed on a first test pad of the first die. A first blocking layer is formed over the first bonding dielectric material. A second bonding dielectric material and a first dummy metal layer are formed over the first blocking layer. The first dummy metal layer and the first test pad are electrically isolated from each other by the first blocking layer. Thereafter, a second bonding structure is formed over a front side of a second die. The first die and the second die are bonded through the first bonding structure and the second bonding structure.
    Type: Application
    Filed: June 5, 2024
    Publication date: October 3, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Jung Yang, Hsien-Wei Chen
  • Publication number: 20240250089
    Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.
    Type: Application
    Filed: April 5, 2024
    Publication date: July 25, 2024
    Inventors: Harry-Hak-Lay Chuang, Wei-Cheng Wu, Chien Hung Liu, Hsin Fu Lin, Hsien Jung Chen, Henry Wang, Tsung-Hao Yeh, Kuo-Ching Huang
  • Publication number: 20240234401
    Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.
    Type: Application
    Filed: April 18, 2023
    Publication date: July 11, 2024
    Inventors: Chien Hung LIU, Yu-Sheng CHEN, Yi Ching ONG, Hsien Jung CHEN, Kuen-Yi CHEN, Kuo-Ching HUANG, Harry-HakLay CHUANG, Wei-Cheng WU, Yu-Jen WANG
  • Patent number: 11978740
    Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: May 7, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Harry-Hak-Lay Chuang, Kuo-Ching Huang, Wei-Cheng Wu, Hsin Fu Lin, Henry Wang, Chien Hung Liu, Tsung-Hao Yeh, Hsien Jung Chen
  • Publication number: 20240136346
    Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.
    Type: Application
    Filed: April 17, 2023
    Publication date: April 25, 2024
    Inventors: Chien Hung LIU, Yu-Sheng CHEN, Yi Ching ONG, Hsien Jung CHEN, Kuen-Yi CHEN, Kuo-Ching HUANG, Harry-HakLay CHUANG, Wei-Cheng WU, Yu-Jen WANG
  • Publication number: 20240105644
    Abstract: A semiconductor die package includes a high dielectric constant (high-k) dielectric layer over a device region of a first semiconductor die that is bonded with a second semiconductor die in a wafer on wafer (WoW) configuration. A through silicon via (TSV) structure may be formed through the device region. The high-k dielectric layer has an intrinsic negative charge polarity that provides a coupling voltage to modify the electric potential in the device region. In particular, the electron carriers in high-k dielectric layer attracts hole charge carriers in device region, which suppresses trap-assist tunnels that result from surface defects formed during etching of the recess for the TSV structure. Accordingly, the high-k dielectric layer described herein reduces the likelihood of (and/or the magnitude of) current leakage in semiconductor devices that are included in the device region of the first semiconductor die.
    Type: Application
    Filed: January 6, 2023
    Publication date: March 28, 2024
    Inventors: Tsung-Hao YEH, Chien Hung LIU, Hsien Jung CHEN, Hsin Heng WANG, Kuo-Ching HUANG
  • Publication number: 20240047508
    Abstract: A semiconductor structure includes an inductive metal line located in a dielectric material layer that overlies a semiconductor substrate and laterally encloses a first area; and an array of first ferromagnetic plates including a first ferromagnetic material and overlying or underlying the inductive metal line. For any first point that is selected within volumes of the first ferromagnetic plates, a respective second point exists within a horizontal surface of the inductive metal line such that a line connecting the first point and the second point is vertical or has a respective first taper angle that is less than 20 degrees with respective to a vertical direction. The magnetic field passing through the first ferromagnetic plates is applied generally along a hard direction of magnetization and the hysteresis effect is minimized.
    Type: Application
    Filed: August 8, 2022
    Publication date: February 8, 2024
    Inventors: Yu-Sheng Chen, Hsien Jung Chen, Kuen-Yi Chen, Chien Hung Liu, Yi Ching Ong, Yu-Jen Wang, Kuo-Ching Huang, Harry-Hak-Lay Chuang
  • Publication number: 20230261004
    Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device on the top semiconductor layer.
    Type: Application
    Filed: February 17, 2022
    Publication date: August 17, 2023
    Inventors: Harry-Hak-Lay CHUANG, Kuo-Ching HUANG, Wei-Cheng WU, Hsin Fu LIN, Henry WANG, Chien Hung LIU, Tsung-Hao YEH, Hsien Jung CHEN
  • Patent number: 10878915
    Abstract: A method for programming a memory device is provided. The memory device includes first to fourth memory cells, in which the first and second memory cells share a first erase gate, and the third and fourth memory cells share a second erase gate. The method includes applying a first voltage to control gates of the first and third memory cell; applying a second voltage to control gates of the second and fourth memory cells, in which the first voltage is higher than the second voltage; applying a third voltage to a select gate of the first memory cell; and applying a fourth voltage to select gates of the second to fourth memory cell, in which the third voltage is higher than the fourth voltage.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Pin Chang, Hsien-Jung Chen, Chien-Hung Liu, Chih-Wei Hung
  • Patent number: 8225805
    Abstract: A protective device for automatic open close umbrellas is revealed. The protective device includes a ratchet mounted in a handle and rotating elastically for retracting or releasing a string, a string whose bottom end is fixed on the ratchet while a top end is fixed on an outer tube of an umbrella shaft or a core tube, and a locking member that is reverse L-shaped and is arranged with an elastic member for turning back therein. The locking member includes an upper part, a lower part, and a middle axle, used as a first-class lever. The upper part is against the bottom of the umbrella shaft so that the fastener can lean against a top surface of the upper part. When the umbrella shaft is gradually folded, the top surface of the upper part of the locking member is separated from the fastener while the bottom of the lower part is locked to one of the ratchet teeth of the ratchet elastically so as to achieve anti-springing effect.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: July 24, 2012
    Inventors: Tsun-Zong Wu, Hsien-Jung Chen
  • Publication number: 20110232707
    Abstract: A protective device for automatic open close umbrellas is revealed. The protective device includes a ratchet mounted in a handle and rotating elastically for retracting or releasing a string, a string whose bottom end is fixed on the ratchet while a top end is fixed on an outer tube of an umbrella shaft or a core tube, and a locking member that is reverse L-shaped and is arranged with an elastic member for turning back therein. The locking member includes an upper part, a lower part, and a middle axle, used as a first-class lever. The upper part is against the bottom of the umbrella shaft so that the fastener can lean against a top surface of the upper part. When the umbrella shaft is gradually folded, the top surface of the upper part of the locking member is separated from the fastener while the bottom of the lower part is locked to one of the ratchet teeth of the ratchet elastically so as to achieve anti-springing effect.
    Type: Application
    Filed: March 29, 2010
    Publication date: September 29, 2011
    Inventors: Tsun-Zong Wu, Hsien-Jung Chen
  • Patent number: 3987151
    Abstract: A process for the production of alkali metal amides is provided wherein liquid ammonia is reacted with an alkali metal under moderate pressure in the presence of an alkali metal azide as catalyst.
    Type: Grant
    Filed: March 20, 1975
    Date of Patent: October 19, 1976
    Assignee: Canadian Industries, Ltd.
    Inventors: Peter John Astrauskas, Guy Michel Blongin, Sherman Hsien-Jung Chen