Abstract: A method of manufacturing the semiconductor device having a dual fully-silicided gate includes the following steps. A substrate having a first transistor and a second transistor formed thereon is provided, wherein the first transistor includes a first gate and a first source/drain and the second transistor includes a second gate and a second source/drain. The gate height of the first gate is different from that of the second gate. A first silicidation process is performed to respectively transform the first gate and the second gate into a first silicided gate and a second silicided gate simultaneously, wherein the material of the first silicided gate is different from that of the second silicided gate.

Abstract: A method of manufacturing a metal-oxide-semiconductor transistor device is disclosed, in which, an insulation region is formed to define the insulation region and an active region, wherein the active region is adjacent to the insulation region and electrically insulated by the insulation region. A selective epitaxial process is performed to form an epitaxial layer on the active region; wherein the epitaxial layer laterally extends onto a surface of a peripheral portion of the insulation region. Thereafter, a doped well is formed in the semiconductor substrate of the active region. A gate structure is formed on the epitaxial layer. Finally, a drain/source region is formed in the semiconductor substrate and the epitaxial layer at a side of the gate structure.

Abstract: A complementary metal-oxide-semiconductor (CMOS) device includes a substrate with a first active region and a second active region; a first gate structure and a second gate structure, respectively disposed on the first active region and the second active region; a first spacer structure and a second spacer structure respectively disposed on sidewalls of the first gate structure and the second gate structure; a first LDD and a second LDD respectively disposed in the substrate at both sides of the first gate structure and the second gate structure; an epitaxial material layer, disposed in the first active region and located on a side of the first LDD; and a passivation layer, disposed on the first gate structure, the first spacer structure, and the first LDD and covering the second active region, wherein the passivation layer comprises a carbon-containing oxynitride layer.

Abstract: A semiconductor device having dual fully-silicided gate is provided, which includes a first transistor, a second transistor, a dielectric layer, and an interlayer insulating layer. The first transistor is disposed on the substrate, which includes a first silicided gate and a first source/drain. The second transistor is disposed on the substrate, which includes a second silicided gate and a second source/drain. The material of the first silicided gate is different from the material of the second silicided gate. The first silicided gate and the second silicided gate are formed in one silicidation process. The dielectric layer completely covers the first transistor and the second transistor. The interlayer insulating layer is disposed on the dielectric layer.

Abstract: A complementary metal-oxide-semiconductor (CMOS) device includes a substrate with a first active region and a second active region; a first gate structure and a second gate structure, respectively disposed on the first active region and the second active region; a first spacer structure and a second spacer structure respectively disposed on sidewalls of the first gate structure and the second gate structure; a first LDD and a second LDD respectively disposed in the substrate at both sides of the first gate structure and the second gate structure; an epitaxial material layer, disposed in the first active region and located on a side of the first LDD; and a passivation layer, disposed on the first gate structure, the first spacer structure, and the first LDD and covering the second active region, wherein the passivation layer comprises a carbon-containing oxynitride layer.

Abstract: A complementary metal-oxide-semiconductor (CMOS) device includes a substrate with a first active region and a second active region; a first gate structure and a second gate structure, respectively disposed on the first active region and the second active region; a first spacer structure and a second spacer structure respectively disposed on sidewalls of the first gate structure and the second gate structure; a first LDD and a second LDD respectively disposed in the substrate at both sides of the first gate structure and the second gate structure; an epitaxial material layer, disposed in the first active region and located on a side of the first LDD; and a passivation layer, disposed on the first gate structure, the first spacer structure, and the first LDD and covering the second active region, wherein the passivation layer comprises a carbon-containing oxynitride layer.

Abstract: A metal-oxide-semiconductor transistor device comprises a semiconductor substrate comprising an active region and an insulation region, a selective epitaxial layer between the active region and a gate structure, wherein a peripheral portion of the epitaxial layer is over a peripheral portion of the insulation region, such that the width of the channel is increased and a drain current is improved.

Abstract: A metal-oxide-semiconductor (MOS) transistor device is provided. The MOS transistor device includes a substrate, a gate structure, a spacer, a source/drain region and a barrier layer. The gate structure is disposed on the substrate. The gate structure includes a gate and a gate dielectric layer disposed between the gate and the substrate. The spacer is disposed on the sidewall of the gate structure. The source/drain region is disposed in the substrate on two sides of the spacer. The barrier layer is disposed around the source/drain region. The source/drain region and the barrier layer are fabricated using an identical material. However, the doping concentration of the source/drain region is larger than the doping concentration of the barrier layer.

Abstract: A metal-oxide-semiconductor (MOS) transistor device is provided. The MOS transistor device includes a substrate, a gate structure, a spacer, a source/drain region and a barrier layer. The gate structure is disposed on the substrate. The gate structure includes a gate and a gate dielectric layer disposed between the gate and the substrate. The spacer is disposed on the sidewall of the gate structure. The source/drain region is disposed in the substrate on two sides of the spacer. The barrier layer is disposed around the source/drain region. The source/drain region and the barrier layer are fabricated using an identical material. However, the doping concentration of the source/drain region is larger than the doping concentration of the barrier layer.

Abstract: A semiconductor fabrication method is provided for forming an opening in a dielectric layer, which can help the resulting opening to be more accurately dimensioned to its specified size without being overly large. By this method, a first dielectric layer is formed from undoped silicate glass (USG) over the substrate, then a second dielectric layer is formed from an acid-resistant dielectric material over the first dielectric layer, and a third dielectric layer is subsequently formed from a thermal-flow dielectric material over the third dielectric layer. A thermal-flow process is performed to slightly planarize the third dielectric layer. Next, an isotropic etch-back process is performed to remove entirely the third dielectric layer and to remove partly the second dielectric layer partly until reaching a predefined plane in the second dielectric layer. A photolithographic and etching process is then performed to form an opening in the combined structure of the first and second dielectric layers.

Abstract: A method of fabricating a shallow trench isolation structure is described. A mask layer is formed on a substrate. The mask layer and the substrate are patterned to form a trench in the substrate. A first deposition step and a second deposition step are performed to form a first isolation layer over the substrate. A third deposition step is performed to form a second isolation layer on the first isolation layer. The second isolation layer has a greater fluidity than the first isolation layer has. A planarization process is performed with the mask layer serving as a stop layer. A portion of the first isolation layer and the mask layer are removed to form the shallow trench isolation structure.

Abstract: A method for manufacturing a shallow trench isolation. A substrate is provided, wherein the substrate has a pad oxide on the substrate and a silicon nitride layer on the pad oxide layer, and a trench penetrates through the silicon oxide layer and the pad oxide layer and into the substrate. A first oxide layer is conformally formed on the silicon nitride layer and in the trench. A rapid thermal process is performed. A second oxide layer is formed on the oxide layer to fill the trench. Portions of the first and the second oxide layers are removed to expose the silicon nitride layer.

Abstract: A method for forming an insulating layer to solve a problem of non-uniform thickness of the insulating layer is provided. The method includes forming a first insulating layer over a substrate preferably by chemical vapor deposition (CVD) at an operation temperature of about 200° C.-350° C. The thickness of the first insulating layer is about 500 Å-5000 Å. A second insulating layer is formed over the first insulating layer preferably by CVD at a temperature of about 350° C.-500° C. The thickness of the second insulating layer is about 1000 Å-10000 Å. The first and the second insulating layers form together as an insulating layer to insulate transistors and isolation structures from the interconnect metal layer.

Abstract: A method of removing a copper oxide layer within a via hole. A copper layer is formed. A dielectric layer is formed on the copper layer. A via hole is formed to penetrate through the dielectric layer and expose a part of the copper layer within the via hole. The exposed copper layer reacts with oxygen in air to form a copper oxide layer. Using 1,1,1,5,5,5-hexafluoro-2,4-pentanedione, the copper oxide layer is removed.

Abstract: The present invention relates to a method of forming a barrier metal layer for a hot Al plug and its structure and more particularly to remarkably ameliorate the performance of a barrier metal layer preventing Al metal used as an interconnection layer from diffusing into a silicon substrate. A barrier metal layer according to the present invention is a stacked structure comprising a top layer of Tungsten (W) formed by a Chemical Vapor Deposition (CVD) method and a bottom layer of TiN. Then, a Al interconnection layer deposited at high temperature fills a plug and finishes a plug structure having advantages of low manufacturing cost and full prevention of Al diffusion.

Abstract: The present invention relates to a method of a sequencial WSi/.alpha.-Si sputtering process, more particularly to a method of in-situ wafer cooling for a sequencial WSi/.alpha.-Si sputtering process. A sputtering process of WSi and a sputtering process of .alpha.-Si are finished in a multi-chamber sputtering apparatus according to the invention; meanwhile, a wafer is cooled down by bolwing of inert gas before a process of sputtering .alpha.-Si starts. Thus, compared to traditional art of finishing WSi/.alpha.-Si sputtering in two apparatus, partial time of vacuuming and venting required in a sputtering process is saved according to the invention, thereby, shortening the production cycle time, reducing the possibility of wafer contamination, and suppressing the fabricating cost.