Abstract: A file managing method for design flows of integrated circuit design includes the following operations: assigning a first file to a first storage address by a processor, in which the first file is generated at a first stage of stages and the files generated in each stage have different versions; assigning a second file to a second storage address by the processor, in which the second file is generated at a second stage of the stages and the second file is generated based on the first file: generating data based on the first file, the second file, the first storage address, and the second storage address, by the processor, to reflect relevance between the first file and the second file; and when the first file or the second file is read, both of the first and second files are shown, based on the relevance data, by the processor.

Abstract: For accomplishing a circuit design, a first physical design is implemented according to a first netlist to obtain a first physical layout of a circuit. The first physical layout of the circuit is processed to obtain a first timing data. The first timing data is then inputted for timing verification of the first netlist. If the first netlist does not pass the verification, the first netlist is modified into a second netlist, while defining a modified portion of the netlist. Then, the modified portion of netlist is processed to obtain a second timing data, and the second timing data is used to overwrite a part of the first timing data. The first physical design is modified into a second physical design according to the second netlist only when the second netlist with the first timing data overwritten by the second timing data passes the timing verification, thereby improving time efficiency.

Abstract: For accomplishing a circuit design, a first physical design is implemented according to a first netlist to obtain a first physical layout of a circuit. The first physical layout of the circuit is processed to obtain a first timing data. The first timing data is then inputted for timing verification of the first netlist. If the first netlist does not pass the verification, the first netlist is modified into a second netlist, while defining a modified portion of the netlist. Then, the modified portion of netlist is processed to obtain a second timing data, and the second timing data is used to overwrite a part of the first timing data. The first physical design is modified into a second physical design according to the second netlist only when the second netlist with the first timing data overwritten by the second timing data passes the timing verification, thereby improving time efficiency.