Patents by Inventor Hsien-Pin Hu

Hsien-Pin Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240222242
    Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.
    Type: Application
    Filed: March 19, 2024
    Publication date: July 4, 2024
    Inventors: Shang-Yun Hou, Hsien-Pin Hu, Sao-Ling Chiu, Wen-Hsin Wei, Ping-Kang Huang, Chih-Ta Shen, Szu-Wei Lu, Ying-Ching Shih, Wen-Chih Chiou, Chi-Hsi Wu, Chen-Hua Yu
  • Publication number: 20240213167
    Abstract: A package structure and method for forming the same are provided. The package structure includes a substrate having a front surface and a back surface, and a die formed on the back surface of the substrate. The package structure includes a first through via structure formed in the substrate, a conductive structure formed in a passivation layer) over the front surface of the substrate. The conductive structure includes a via portion in direct contact with the substrate. The package structure includes a connector (formed over the via portion, wherein the connector includes an extending portion directly on a recessed top surface of the via portion.
    Type: Application
    Filed: February 5, 2024
    Publication date: June 27, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Kai CHENG, Tsung-Shu LIN, Tsung-Yu CHEN, Hsien-Pin HU, Wen-Hsin WEI
  • Patent number: 12021006
    Abstract: An apparatus for manufacturing packaged semiconductor devices includes a lower plate having package platforms and clamp guide pins to align an upper plate with the lower plate, and a boat tray having windows configured to receive package devices, and a plurality of upper plates configured to be aligned to respective windows and respective package platforms. Clamping force can be applied by fasteners configured to generate a downward force upon the upper plate. Package devices on the platforms are thus subjected to a clamping force. Load cells measure the clamping force so adjustments can be made.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: June 25, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wensen Hung, Tsung-Yu Chen, Tsung-Shu Lin, Chen-Hsiang Lao, Wen-Hsin Wei, Hsien-Pin Hu
  • Patent number: 12015023
    Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: June 18, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Yun Hou, Sung-Hui Huang, Kuan-Yu Huang, Hsien-Pin Hu, Yushun Lin, Heh-Chang Huang, Hsing-Kuo Hsia, Chih-Chieh Hung, Ying-Ching Shih, Chin-Fu Kao, Wen-Hsin Wei, Li-Chung Kuo, Chi-Hsi Wu, Chen-Hua Yu
  • Patent number: 11996371
    Abstract: Embodiments include packages and methods for forming packages which include interposers having a substrate made of a dielectric material. The interposers may also include a redistribution structure over the substrate which includes metallization patterns which are stitched together in a patterning process which includes multiple lateral overlapping patterning exposures.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shang-Yun Hou, Weiming Chris Chen, Kuo-Chiang Ting, Hsien-Pin Hu, Wen-Chih Chiou, Chen-Hua Yu
  • Patent number: 11967546
    Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Yun Hou, Hsien-Pin Hu, Sao-Ling Chiu, Wen-Hsin Wei, Ping-Kang Huang, Chih-Ta Shen, Szu-Wei Lu, Ying-Ching Shih, Wen-Chih Chiou, Chi-Hsi Wu, Chen-Hua Yu
  • Publication number: 20240105632
    Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 28, 2024
    Inventors: Hsien-Pin Hu, Chen-Hua Yu, Ming-Fa Chen, Jing-Cheng Lin, Jiun Ren Lai, Yung-Chi Lin
  • Publication number: 20240105627
    Abstract: Semiconductor devices and methods of manufacture are provided. In embodiments the semiconductor device includes a substrate, a first interposer bonded to the substrate, a second interposer bonded to the substrate, a bridge component electrically connecting the first interposer to the second interposer, two or more first dies bonded to the first interposer; and two or more second dies bonded to the second interposer.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 28, 2024
    Inventors: Shang-Yun Hou, Hsien-Pin Hu
  • Publication number: 20240088093
    Abstract: In an embodiment, a method includes: attaching a package component to a package substrate, the package component includes: a first die being disposed over an interposer; a second die being disposed over the interposer and laterally adjacent to the first die; and an encapsulant being disposed around the first die and the second die; attaching a thermal interface material to the first die and the second die; and attaching a lid structure to the package substrate, the lid structure includes: a lid cap being disposed over the thermal interface material; and a plurality of lid feet connecting the lid cap to the package substrate, in a plan view the plurality of lid feet forming a discontinuous loop around the package component.
    Type: Application
    Filed: January 4, 2023
    Publication date: March 14, 2024
    Inventors: Wensen Hung, Tsung-Yu Chen, Wen-Hsin Wei, Hsien-Pin Hu
  • Patent number: 11923310
    Abstract: A package structure and method for forming the same are provided. The package structure includes a first through via structure formed in a substrate and a semiconductor die formed below the first through via structure. The package structure further includes a conductive structure formed in a passivation layer over the substrate. The conductive structure includes a first via portion and a second via portion, the first via portion is directly over the first through via structure, and there is no conductive material directly below and in direct contact with the second via portion.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Kai Cheng, Tsung-Shu Lin, Tsung-Yu Chen, Hsien-Pin Hu, Wen-Hsin Wei
  • Patent number: 11854990
    Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Pin Hu, Chen-Hua Yu, Ming-Fa Chen, Jing-Cheng Lin, Jiun Ren Lai, Yung-Chi Lin
  • Patent number: 11854983
    Abstract: Semiconductor devices and methods of manufacture are provided. In embodiments the semiconductor device includes a substrate, a first interposer bonded to the substrate, a second interposer bonded to the substrate, a bridge component electrically connecting the first interposer to the second interposer, two or more first dies bonded to the first interposer; and two or more second dies bonded to the second interposer.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Yun Hou, Hsien-Pin Hu
  • Patent number: 11830745
    Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: November 28, 2023
    Assignee: TAIWANN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Wei Chiu, Cheng-Hsien Hsieh, Hsien-Pin Hu, Kuo-Ching Hsu, Shang-Yun Hou, Shin-Puu Jeng
  • Publication number: 20230369162
    Abstract: An apparatus for manufacturing packaged semiconductor devices includes a lower plate having package platforms and clamp guide pins to align an upper plate with the lower plate, and a boat tray having windows configured to receive package devices, and a plurality of upper plates configured to be aligned to respective windows and respective package platforms. Clamping force can be applied by fasteners configured to generate a downward force upon the upper plate. Package devices on the platforms are thus subjected to a clamping force. Load cells measure the clamping force so adjustments can be made.
    Type: Application
    Filed: July 28, 2023
    Publication date: November 16, 2023
    Inventors: Wensen Hung, Tsung-Yu Chen, Tsung-Shu Lin, Chen-Hsiang Lao, Wen-Hsin Wei, Hsien-Pin Hu
  • Patent number: 11810833
    Abstract: A packaged semiconductor device and a method and apparatus for forming the same are disclosed. In an embodiment, a method includes bonding a device die to a first surface of a substrate; depositing an adhesive on the first surface of the substrate; depositing a thermal interface material on a surface of the device die opposite the substrate; placing a lid over the device die and the substrate, the lid contacting the adhesive and the thermal interface material; applying a clamping force to the lid and the substrate; and while applying the clamping force, curing the adhesive and the thermal interface material.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: November 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wensen Hung, Tsung-Yu Chen, Tsung-Shu Lin, Chen-Hsiang Lao, Wen-Hsin Wei, Hsien-Pin Hu
  • Publication number: 20230260896
    Abstract: A device package including an interposer. The interposer comprising: a semiconductor substrate; first through vias extending through the semiconductor substrate; an interconnect structure comprising: a first metallization pattern in an inorganic insulating material; and a passivation film over the first metallization pattern; and a first redistribution structure over the passivation film. The first redistribution structure comprising a second metallization pattern in an organic insulating material. The device package further including an integrated circuit die over and attached to the interposer; and a first encapsulant around the integrated circuit die.
    Type: Application
    Filed: June 10, 2022
    Publication date: August 17, 2023
    Inventors: Hsien-Pin Hu, Shang-Yun Hou, Shih-Wen Huang
  • Patent number: 11728254
    Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shang-Yun Hou, Hsien-Pin Hu, Sao-Ling Chiu, Wen-Hsin Wei, Ping-Kang Huang, Chih-Ta Shen, Szu-Wei Lu, Ying-Ching Shih, Wen-Chih Chiou, Chi-Hsi Wu, Chen-Hua Yu
  • Patent number: 11682593
    Abstract: An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: June 20, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzuan-Horng Liu, Chen-Hua Yu, Hsien-Pin Hu, Tzu-Yu Wang, Wei-Cheng Wu, Shang-Yun Hou, Shin-Puu Jeng
  • Patent number: 11569172
    Abstract: Semiconductor devices and methods of manufacture are provided. In embodiments the semiconductor device includes a substrate, a first interposer bonded to the substrate, a second interposer bonded to the substrate, a bridge component electrically connecting the first interposer to the second interposer, two or more first dies bonded to the first interposer; and two or more second dies bonded to the second interposer.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: January 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shang-Yun Hou, Hsien-Pin Hu
  • Patent number: 11527454
    Abstract: An embodiment is a method including: attaching a first die to a first side of a first component using first electrical connectors, attaching a first side of a second die to first side of the first component using second electrical connectors, attaching a dummy die to the first side of the first component in a scribe line region of the first component, adhering a cover structure to a second side of the second die, and singulating the first component and the dummy die to form a package structure.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: December 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Hsin Wei, Chi-Hsi Wu, Shang-Yun Hou, Jing-Cheng Lin, Hsien-Pin Hu, Ying-Ching Shih, Szu-Wei Lu