Abstract: A packaged semiconductor device includes a semiconductor substrate, a metal pad, a metal base, a polymer insulating layer, a copper-containing structure and a conductive bump. The metal pad and the metal base are disposed on the semiconductor substrate. The polymer insulating layer overlies the metal base and the semiconductor substrate. The copper-containing structure is disposed over the polymer insulating layer, and includes a support structure and a post-passivation interconnect (PPI) line. The support structure is aligned with the metal base. The PPI line is located partially within the support structure, and extends out through an opening of the support structure, in which a top of the support structure is elevated higher than a top of the PPI line. The conductive bump is held by the support structure.

Abstract: A transmission shaft set including a plurality of transmission shaft structures is disclosed. Each transmission shaft structure includes a metal pin connecting shaft and a base. The metal pin connecting shaft includes an arc part, a fastening block, a plurality of electrically connecting parts and a plurality of electrically connecting metal pins. The plurality of electrically connecting parts are located on the arc part. The plurality of electrically connecting metal pins are located in the fastening block and electrically connected to the plurality of electrically connecting parts. The base is fastened to the metal pin connecting shaft and includes a fastening groove, at least one fastening part and at least one column. The fastening groove is used for fastening the fastening block. The fastening part is located near the fastening groove. The column is located near the fastening groove and the fastening part.

Abstract: A semiconductor package structure, comprises a substrate, a die region having one or more dies disposed on the substrate, and at least one stress relief structure disposed at one or more corners of the substrate, the at least one stress relief structure being adjacent to at least one die of the one or more dies.

Abstract: A semiconductor device including a dielectric layer formed on the surface of a post-passivation interconnect (PPI) structures. A polymer layer is formed on the dielectric layer and patterned with an opening to expose a portion of the dielectric layer. The exposed portion of the dielectric layer is then removed to expose a portion of the PPI structure. A solder bump is then formed over and electrically connected to the first portion of the PPI structure.

Abstract: Disclosed herein is a device comprising a first redistribution layer (RDL) having first lands disposed on a bottom surface of the first RDL and active contact pads disposed on a top surface of the first RDL. The first RDL electrically connects the first lands to the active contact pads. A molding compound layer is disposed on the top surface of the first RDL. Active vias extend through the molding compound layer and are in electrical contact with the active contact pads. Dummy vias extending through the molding compound layer. Top surfaces of the active vias and top surfaces of the dummy vias are substantially planar with a top surface of the molding compound layer, and the dummy vias are electrically insulated from the active vias and the first lands.

Abstract: A device comprises a top package mounted on a bottom package through a joint structure, wherein the joint structure comprises a solder ball of the top package coupled to a metal structure embedded in the bottom package and an epoxy protection layer having a first edge in direct contact with a top surface of the bottom package and a second edge surrounding a lower portion of the solder ball.

Abstract: A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.

Abstract: A seal ring for semiconductor devices is provided with embedded decoupling capacitors. The seal ring peripherally surrounds an integrated circuit chip in a seal ring area. The at least one embedded decoupling capacitor may include MOS capacitors, varactors, MOM capacitors and interdigitized capacitors with multiple capacitor plates coupled together. The opposed capacitor plates are coupled to different potentials and may advantageously be coupled to Vdd and Vss.

Abstract: A first package is bonded to a second package with a structural member located between the first package and the second package for structural support. In an embodiment the structural member is a plate or one or more conductive balls. Once the structural member is in place, the first package is bonded to the second package.

Abstract: Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, and an external connector on the connector support metallization. The redistribution structure includes a dielectric layer disposed distally from the encapsulant and the integrated circuit die. The connector support metallization has a first portion on a surface of the dielectric layer and has a second portion extending in an opening through the dielectric layer. The first portion of the connector support metallization has a sloped sidewall extending in a direction away from the surface of the dielectric layer.

Abstract: Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, a dummy pattern, a second dielectric layer, and an external connector on the connector support metallization. The redistribution structure comprises a first dielectric layer having a first surface disposed distally from the encapsulant and the integrated circuit die. The dummy pattern is on the first surface of the first dielectric layer and around the connector support metallization. The second dielectric layer is on the first surface of the first dielectric layer and on at least a portion of the dummy pattern. The second dielectric layer does not contact the connector support metallization.

Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a package substrate bonded to a first side of the first package with by a first set of connectors. The semiconductor package further includes a surface mount device mounted to the first side of the first package, the surface mount device consisting essentially of one or more passive devices.

Abstract: Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer and/or polymer layer disposed over the substrate and a portion of the contact pad. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to an exposed portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element includes line having a width greater than the PPI line.

Abstract: A method and apparatus for a reinforced package are provided. A package component may be electrically coupled to a device through a plurality of electrical connections. A molding underfill may be interposed between the package component and the device and may encapsulate the plurality of electrical connections or a subset of the plurality of electrical connections between the package component and the device. The package component may also include a molding compound. The plurality of the electrical connections may extend through the molding compound with the molding underfill interposed between the molding compound and the device to encapsulate the plurality of electrical connections or a subset of the plurality of electrical connections between the package component and the device. The molding underfill may extend up one or more sides of the package component.

Abstract: A device includes a first package component, and a second package component underlying the first package component. The second package component includes a first electrical connector at a top surface of the second package component, wherein the first electrical connector is bonded to the first package component. The second package component further includes a second electrical connector at the top surface of the second package component, wherein no package component is overlying and bonded to the second electrical connector.

Abstract: Methods of forming and structures of packages are discussed herein. In an embodiment, a method includes forming a back side redistribution structure, and after forming the back side redistribution structure, adhering a first integrated circuit die to the back side redistribution structure. The method further includes encapsulating the first integrated circuit die on the back side redistribution structure with an encapsulant, forming a front side redistribution structure on the encapsulant, and electrically coupling a second integrated circuit die to the first integrated circuit die. The second integrated circuit die is electrically coupled to the first integrated circuit die through first external electrical connectors mechanically attached to the front side redistribution structure.

Abstract: A device and method of manufacture is provided that utilize recessed regions along a package edge. For example, in an integrated fan-out package, the dielectric layers, e.g., the polymer layers, of the redistribution layers are removed along the scribe line such that after singulation the dielectric layers are recessed back from the edges of the die. The corner regions may be recessed further. The recessed regions may be triangular, rounded, or other shape. In some embodiments one or more of the corner regions may be recessed further relative to the remaining corner regions. The redistribution layers may be recessed along one or both of the front side redistribution layers and the backside redistribution layers.

Abstract: Disclosed herein is an interconnect apparatus comprising a substrate having a land disposed thereon and a passivation layer disposed over the substrate and over a portion of the land. An insulation layer is disposed over the substrate and has an opening disposed over at least a portion of the land. A conductive layer is disposed over a portion of the passivation layer and in electrical contact with the land. The conductive layer has a portion extending over at least a portion of the insulation layer. The conductive layer comprises a contact portion disposed over at least a portion of the land. The insulation layer avoids extending between the land and the contact portion. A protective layer may be disposed over at least a portion of the conductive layer and may optionally have a thickness of at least 7 ?m.

Abstract: According to an exemplary embodiment, a semiconductor package is provided. The semiconductor package includes: a backside redistribution layer; at least one component, disposed over and connected to the backside redistribution layer; at least one chip adjacent to the at least one component; a molding compound disposed between the at least one chip and the at least one component; a via, disposed in the molding compound and connected to the backside redistribution layer; and a front redistribution layer, disposed over the chip and the via, wherein the chip and the at least one component are connected by using the backside redistribution layer, the via and the front redistribution layer.

Abstract: According to an exemplary embodiment, a semiconductor package is provided. The semiconductor package includes: a chip having a plurality of joint pads; a component having a plurality of metal caps on one side and having a grinded surface on the other side, wherein the metal caps are in contact with the joint pads of the chip.