Abstract: An apparatus and a method for detecting a lock error in a sensorless motor are disclosed, where the apparatus includes a multiplexer, a negative booster, a comparator and a timer. The multiplexer can receive a coil voltage from the sensorless motor. The negative booster can receive a neutralizing voltage from the sensorless motor and drop the neutralizing voltage. The comparator can compare the coil voltage with the dropped neutralizing voltage for outputting a zero-crossing signal. The timer can count time duration during the zero-crossing signal maintained at the a logic level and determine the lock error in the sensorless motor when the time duration exceeds a predetermined period.

Abstract: An apparatus and a method for driving a sensorless motor are described and shown in the specification and drawings, where the method includes steps as follows. First, a control signal is acquired, where the control signal has information of a predetermined rotational speed. Next, energy is supplied and progressively increased to the sensorless motor, so as to rotate a rotor of the sensorless motor. Then, a position of the rotor is detected. Finally, the energy is gradually regulated so that the sensorless motor is maintained at the predetermined rotational speed.

Abstract: A high-side driving circuit is provided, where Q terminal and Q terminal of the latch circuit respectively feed back to the first switch and the second switch, which may control asymmetric impedance, such that the high-side driving circuit can prevent noise.

Abstract: A transmission mechanism with intermittent output movement includes an output shaft rotatably mounted to first and second cams and a sun gear mounted to the output shaft. A first rocker includes a first planet gear meshed with the sun gear and first and second rollers rotatably mounted on opposite sides of the first planet gear and respectively in contact with the first and second cams. A second rocker includes a second planet gear meshed with the sun gear. An end of a first connecting rod is mounted to the first rocker. An end of a second connecting rod is mounted to the second rocker. Two ends of a link are rotatably mounted to the other ends of the first and second connecting rods. A planet gear carrier is mounted to an input shaft coaxial to the input shaft and includes an end rotatably mounted to the first rocker.

Abstract: A nitride trapping memory device includes a comparator, a bias unit, a memory cell, a cycling cell, a compensation cell and a control unit. The comparator has a reference voltage. The bias unit is for outputting a bias voltage to the comparator, and the comparator outputs a bit value according to comparison of the bias voltage and the reference voltage. The memory cell is connected to the bias unit via a first switch. The cycling cell is connected to the bias unit via a second switch. The compensation cell is connected to the bias unit via a third switch. The control unit is for controlling the cycling cell and the compensation cell according to the bit value.

Abstract: The present invention provides a semiconductor device package, comprising a die having a back surface and an active surface formed thereon; an adhesive layer formed on the back surface of the die; a protection substrate formed on the adhesive layer; and a plurality of bumps formed on the active surface of the die for electrically connection. The present invention further provides a method for forming a semiconductor device package, comprising providing a plurality of die having a back surface and an active surface on a wafer; forming an adhesive layer on the back surface of the die; forming a protection substrates on the adhesive layer; forming a plurality of bumps on the active surface of each die; and dicing the plurality of die into individual die for singulation.

Abstract: A high-side driving circuit is provided, where Q terminal and Q terminal of the latch circuit respectively feed back to the first switch and the second switch, which may control asymmetric impedance, such that the high-side driving circuit can prevent noise.

Abstract: The present invention disclosed a first multi-die package structure for semiconductor devices, the structure comprises a substrate having die receiving window and inter-connecting through holes formed therein; a first level semiconductor die formed under a second level semiconductor die by back-to-back scheme and within the die receiving window, wherein the first multi-die package includes first level contact pads formed under the first level semiconductor die having a first level build up layer formed there-under to couple to a first bonding pads of the first level semiconductor die; a second level contact pads formed on the second level semiconductor die having a second level build up layer formed thereon to couple to second bonding pads of the second level semiconductor die; and conductive bumps formed under the first level build up layer.

Abstract: The present invention provides a semiconductor device package having multi-chips with side-by-side configuration comprising a substrate with die receiving through holes, connecting through holes structure and first contact pads on an upper surface and second contact pads on a lower surface of the substrate. A first die having first bonding pads and a second die having second bonding pads are respectively disposed within the die receiving through holes. The first adhesion material is formed under the first and second die and the substrate, and the second adhesion material is filled in the gap between the first and second die and sidewall of the die receiving though holes of the substrate. Further, bonding wires are formed to couple between the first bonding pads and the first contact pads, between the second bonding pads and the first contact pads. A dielectric layer is formed on the bonding wires, the first and second die and the substrate.

Abstract: The interconnecting structure for a semiconductor die assembly comprises a build-up layers having RDL formed therein formed over a die having die pads formed thereon, wherein the RDL is coupled to the die pads; an isolation base having ball openings attached over the build-up layer to expose ball pads within the build-up layers; and conductive balls placed into the ball openings of the isolation base and attached on the ball pads within the build-up layers.

Abstract: The interconnecting structure for a semiconductor die assembly comprises a build-up layers having RDL formed therein formed over a die having die pads formed thereon, wherein the RDL is coupled to the die pads; an isolation base having ball openings attached over the build-up layer to expose ball pads within the build-up layers; and conductive balls placed into the ball openings of the isolation base and attached on the ball pads within the build-up layers.

Abstract: The present invention provides a semiconductor device package, comprising a die having a back surface and an active surface formed thereon; an adhesive layer formed on the back surface of the die; a protection substrate formed on the adhesive layer; and a plurality of bumps formed on the active surface of the die for electrically connection. The present invention further provides a method for forming a semiconductor device package, comprising providing a plurality of die having a back surface and an active surface on a wafer; forming an adhesive layer on the back surface of the die; forming a protection substrates on the adhesive layer; forming a plurality of bumps on the active surface of each die; and dicing the plurality of die into individual die for singulation.

Abstract: The present invention provides a semiconductor device package, comprising a die having a back surface and an active surface formed thereon; an adhesive layer formed on the back surface of the die; a protection substrate formed on the adhesive layer; and a plurality of bumps formed on the active surface of the die for electrically connection. The present invention further provides a method for forming a semiconductor device package, comprising providing a plurality of die having a back surface and an active surface on a wafer; forming an adhesive layer on the back surface of the die; forming a protection substrates on the adhesive layer; forming a plurality of bumps on the active surface of each die; and dicing the plurality of die into individual die for singulation.

Abstract: The present invention provides an apparatus and a method for panel/wafer molding. The present invention discloses a base with a first separation layer, an upper molding base with a second separation layer, a cheap molding layer and a vacuum panel bonding machine for bonding, a curing unit, a cleaning unit and a separating unit; wherein upper molding base is rectangular or round. Therefore the present invention providing a simple, cheap universal panel/wafer molding apparatus for a round or rectangular type panel, and does no harm to the chip active surface.

Abstract: The present invention provides a semiconductor device package having multi-chips with side-by-side configuration comprising a substrate with die receiving through holes, connecting through holes structure and first contact pads on an upper surface and second contact pads on a lower surface of the substrate. A first die having first bonding pads and a second die having second bonding pads are respectively disposed within the die receiving through holes. The first adhesion material is formed under the first and second die and the substrate, and the second adhesion material is filled in the gap between the first and second die and sidewall of the die receiving though holes of the substrate. Further, bonding wires are formed to couple between the first bonding pads and the first contact pads, between the second bonding pads and the first contact pads. A dielectric layer is formed on the bonding wires, the first and second die and the substrate.

Abstract: The present invention provides an apparatus and a method for self chip redistribution. The apparatus of the present invention comprises a glass base on which a trench and a cavity formed by a layer of photo resistance. Chips are picked from a sawed wafer and placed on the glass base and moved by fluid flow to the front of index bar. The glass base and the index bar vibrate with low frequency to fill chips into chip cavities. The present invention further provides a method for self chip redistribution, comprising providing a self redistribution tool, transferring redistributed chips onto a panel forming tool, forming a chip panel and separating said chip panel from panel forming tool.

Abstract: The present invention provides a semiconductor device package comprising a substrate with at lease a pre-formed die receiving cavity formed and terminal contact metal pads formed within an upper surface of the substrate. At lease a first die is disposed within the die receiving cavity. A first dielectric layer is formed on the first die and the substrate and refilled into a gap between the first die and the substrate to absorb thermal mechanical stress there between. A first re-distribution layer (RDL) is formed on the first dielectric layer and coupled to the first die. A second dielectric layer is formed on the first RDL, and then a second die is disposed on the second dielectric layer and surrounded by core pastes having through holes thereon. A second re-distribution layer (RDL) is formed on the core pastes to fill the through holes, and then a third dielectric layer formed on the second RDL.

Abstract: A structure of semiconductor device package having inter-adhesion with gap comprising: a chip with bonding pads and a sensor area embedded into a substrate with die window and inter-connecting through holes, wherein a RDL is formed over the substrate for coupling between the bonding pads and the inter-connecting through holes; a multiple rings (dam bar) formed over the substrate, the RDL, and the bonding pads area except the sensor area; an adhesive glues fill into the space of the multiple ring except the sensor area; and a transparency material bonded on the top of the multiple ring and the adhesive glues, wherein the adhesive glues adhesion between the transparency material and the multiple rings.

Abstract: A nitride trapping memory device includes a comparator, a bias unit, a memory cell, a cycling cell, a compensation cell and a control unit. The comparator has a reference voltage. The bias unit is for outputting a bias voltage to the comparator, and the comparator outputs a bit value according to comparison of the bias voltage and the reference voltage. The memory cell is connected to the bias unit via a first switch. The cycling cell is connected to the bias unit via a second switch. The compensation cell is connected to the bias unit via a third switch. The control unit is for controlling the cycling cell and the compensation cell according to the bit value.

Abstract: The present invention provides a semiconductor device package with the die receiving through hole and connecting through holes structure comprising a substrate with a die receiving through hole, connecting through holes structure and first contact pads on an upper surface and second contact pads on a lower surface of the substrate. A die is disposed within the die receiving through hole. A first adhesion material is formed under the die and a second adhesion material is filled in the gap between the die and sidewall of the die receiving though hole of the substrate. Further, a bonding wire is formed to couple and the bonding pads and the first contact pads. A dielectric layer is formed on the bonding wire, the die and the substrate.