Patents by Inventor Hsien Wu

Hsien Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12389654
    Abstract: A device includes a channel layer, a gate structure, a first gate spacer, and a second gate spacer. The gate structure wraps around the channel layer. The first gate spacer and the second gate spacer are on opposite sides of the gate structure. The first gate spacer has a first portion and a second portion between the gate structure and the first portion of the first gate spacer, and a dopant concentration of the second portion of the first gate spacer is greater than a dopant concentration of the first portion of the first gate spacer.
    Type: Grant
    Filed: September 21, 2023
    Date of Patent: August 12, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Cheng-Hsien Wu
  • Publication number: 20250238829
    Abstract: Techniques for training a price prediction model are disclosed. An example method includes receiving historical transaction data comprising a plurality of transactions, each transaction comprising a plurality of attributes and a transaction price. The method also includes processing the historical transaction data to generate training data comprising features extracted from the plurality of attributes and price indices generated from the transaction price. The method also includes training, by a processing device, a price prediction model using the training data, wherein training the price prediction model comprises training a neural network to generate a mapping between the features and the price indices, and wherein the features used to train the neural network are not segmented and correspond with a plurality of products, product types, geographies, and customer sizes.
    Type: Application
    Filed: January 22, 2024
    Publication date: July 24, 2025
    Inventors: Mohit Mahajan, Yan Xu, Wenshen Song, Royce Kallesen, Jerry Guan, Manu Chaudhary, Zhaoyang Zhang, Chih-Hsien Wu, Yuanyuan Liu, Jonas Rauch
  • Publication number: 20250236079
    Abstract: A thermoplastic fiber composite film manufacturing mechanism and method are provided. The mechanism includes a substrate outputting module, a fiber material outputting module, and a pressing module. The substrate outputting module continuously outputs a film-shaped molten plastic substrate along an output direction. The fiber material outputting module is disposed on one side of the substrate outputting module. The fiber material outputting module continuously outputs a fiber sheet material. The pressing module is disposed on one side of the fiber material outputting module away from the substrate outputting module. The pressing module has a first and a second rollers neighboring each other, with a pressing area formed therebetween. The plastic substrate and the fiber sheet material move to the pressing area; the first and second rollers press the plastic substrate and the fiber sheet material together in parallel into a composite film.
    Type: Application
    Filed: January 24, 2024
    Publication date: July 24, 2025
    Inventors: Chun-Hsien Wu, Chun-Ye Wu
  • Patent number: 12363330
    Abstract: An image processing device includes an image encoder, a memory and an image decoder. The image encoder receives an input image frame, retrieves luminance information and chrominance information from the input image frame, respectively, encodes the luminance information to generate an encoded luminance frame, and encodes the chrominance information to generate an encoded chrominance frame. The memory includes a first memory portion, a second memory portion and a third memory portion. The first memory portion stores the encoded luminance frame, and the second memory portion or the third memory portion stores the encoded chrominance frame. The image decoder reads the encoded luminance frame from the first memory portion to perform decoding, and reads the encoded chrominance frame from the second memory portion or the third memory portion for decoding.
    Type: Grant
    Filed: April 17, 2023
    Date of Patent: July 15, 2025
    Assignee: Realtek Semiconductor Corp.
    Inventors: Yi-Chen Tseng, Po-Hsien Wu
  • Publication number: 20250218707
    Abstract: A button module includes a first electronic element, a pressing element, a second electronic element, and an operation element. The pressing element has a pressing part and a first actuation part. The pressing part has a through-hole. The pressing part moves relative to the first electronic element in a pressing direction. The pressing part drives the first actuation part to move when the pressing part moves so that the first actuation part actuates the first electronic element. The operation element has a driven part and a second actuation part. The second actuation part actuates the second electronic element. The driven part moves relative to the pressing part in an operation direction. The driven part drives the second actuation part to move when the driven part moves so that the second actuation part actuates the second electronic element. A projection device with the button module is also provided.
    Type: Application
    Filed: December 26, 2024
    Publication date: July 3, 2025
    Inventors: CHIEN-CHUNG LIAO, CHANG-YUNG CHEN, CHUN-HSIEN WU
  • Publication number: 20250216833
    Abstract: An autonomous evaluation method and an autonomous evaluation device for semiconductor smart manufacturing are provided. The autonomous evaluation method for the semiconductor smart manufacturing includes the following steps. For each of a plurality of apparatuses, a task completion ratio of each of a plurality of automation functions implemented in a plurality process tasks is analyzed. The task completion ratios of the automation functions are mapped to an evaluation matrix to obtain a depth level corresponding to each of the apparatuses. A plurality of expansion ratios corresponding to the depth levels of the apparatuses are analyzed. A comprehensive indicator is analyzed according to the depth levels and the expansion ratios.
    Type: Application
    Filed: January 26, 2024
    Publication date: July 3, 2025
    Inventors: Yung-Chien KUNG, Li-Hsin YANG, Chung-Hsien WU, Pang-Min WANG
  • Publication number: 20250221317
    Abstract: A memory device includes a spin-orbit torque (“SOT”) conductor, a magnetic tunneling junction (“MTJ”) structure above the SOT conductor, a two-terminal read selector above the MTJ structure, a two-terminal write selector above the MTJ structure, and a bit line below the SOT conductor. The two-terminal read selector is conductively connected to the pinned layer in the MTJ structure. The two-terminal write selector is conductively connected to a first terminal of the SOT conductor. The bit line is conductively connected to a second terminal of the SOT conductor.
    Type: Application
    Filed: April 3, 2024
    Publication date: July 3, 2025
    Inventors: Elia AMBROSI, MingYuan SONG, Cheng-Hsien WU, Xinyu BAO
  • Publication number: 20250218940
    Abstract: A method of fabricating a semiconductor structure provided herein includes providing a thick-metal density range for a model structure, wherein the model structure includes a wafer substrate, and layers of metal patterns stacking on the wafer substrate; modifying the thick-metal density range to constrain a warpage range of the model structure toward a target range of warpage; and fabricating the semiconductor structure by forming the layers of metal patterns on the wafer substrate, wherein a thick-metal layer among the layers of metal patterns is formed based on the modified thick-metal density range, and a thickness of the thick-metal layer is twice or more of a thickness of one of the layers of metal patterns next to the thick-metal layer. A semiconductor structure fabricating by using the above method is further provided.
    Type: Application
    Filed: December 27, 2023
    Publication date: July 3, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Ling Chang, Cheng-Hsien WU, Man-Yun WU, Yu-Bey Wu, Wen-Chiung Tu, Chen-Chiu Huang, Dian-Hau Chen, Chung-Yi Lin, Ching-Feng Sung, Hsiu-Chia Kuo
  • Patent number: 12347193
    Abstract: A dynamic image processing method, executed by an electronic device communicating with a photographing device and reading an executable code is introduced. The method includes the steps of identifying the preset object, image filtering and forming a concatenated video. In the step of image filtering, a filter condition is set, the filter condition includes that the preset object appears in a focus area of the initial image, and when the preset object in the initial image meets the filter condition, a catch moment in the initial image is selected. In the step of forming a concatenated video, at least one video clip in the initial image is selected according to the catch moment, and the at least one video clip is assembled to form the concatenated video. An electronic device, a terminal device and a mobile communication device are also introduced.
    Type: Grant
    Filed: August 24, 2022
    Date of Patent: July 1, 2025
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Pin-Yu Chou, Yu-Ning Chang, Yueh-Hua Lee, Ming-Hsien Wu, Yu-Syuan Huang
  • Publication number: 20250210498
    Abstract: A repackaging structure includes a substrate, at least one chip, a dielectric body, an electrical element and at least one conductive pillar. The substrate includes a plate, a plurality of mounting pads and a plurality of corresponding pads. The corresponding pads and the mounting pads are disposed on opposite surfaces of the plate. The corresponding pads correspond to the mounting pads. The chip is mounted on the substrate. The chip includes a plurality of chip leads. The chip leads are mounted on the mounting pads. The dielectric body covers the chip. The electrical element is disposed on the dielectric body. The conductive pillar electrically connects the electrical element and the substrate.
    Type: Application
    Filed: December 26, 2023
    Publication date: June 26, 2025
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shih-Hsien WU, Hsiu-Cheng CHANG
  • Patent number: 12342548
    Abstract: An ovonic threshold switch (OTS) selector and a memory device including the OTS selector is provided. The OTS selector includes a switching layer formed of a GeCTe compound further doped with one or both of nitrogen and silicon, and exhibits improved thermal stability and electrical performance.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: June 24, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Min Lee, Cheng-Hsien Wu, Cheng-Chun Chang, Elia Ambrosi, Hengyuan Lee, Ying-Yu Chen, Xinyu Bao, Tung-Ying Lee
  • Publication number: 20250199055
    Abstract: A detection system is provided for detecting an element under test. The detection system includes an illumination module, a sensing module, and a processing part. The illumination module provides an illumination beam to the element under test. The illumination beam includes sub-beams of different wavelengths. The sensing module senses the element under test to obtain an electrical signal, and includes a carrier mechanism, a first substrate, a control layer, a sensing layer, and an electrical connection element. The sensing layer is disposed on a first surface of the first substrate, and has a sensing surface that is the surface closest to the element under test in the sensing module. The electrical connection element is electrically connected to the sensing layer and the control layer. The processing part is electrically connected to the illumination module and the sensing module, and configured to generate a sensing result according to the electrical signal.
    Type: Application
    Filed: December 3, 2024
    Publication date: June 19, 2025
    Applicant: Industrial Technology Research Institute
    Inventors: Fu-An Tu, Ming-Hsien Wu
  • Patent number: 12334147
    Abstract: First fire operations for an ovonic threshold switch (OTS) selector is provided. A first fire operation includes setting a peak amplitude of a voltage pulse, and performing at least one cycle, including: providing the voltage pulse to the OTS selector; sensing an output current passing through the OTS selector in response to the received voltage pulse; comparing a peak amplitude of the voltage pulse with a maximum peak amplitude ensuring initialization of the OTS selector; ending the first fire operation if the peak amplitude reaches the maximum peak amplitude; comparing the output current with a target current indicative of initialization of the OTS selector if the peak amplitude is lower than the maximum peak amplitude; ending the first fire operation if the output current reaches the target current; and setting another voltage pulse with a greater peak amplitude if the output current is lower than the target current.
    Type: Grant
    Filed: February 19, 2024
    Date of Patent: June 17, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Elia Ambrosi, Cheng-Hsien Wu, Hengyuan Lee, Chien-Min Lee, Xinyu Bao
  • Patent number: 12336213
    Abstract: A multi-gate semiconductor device includes a plurality of nanostructures vertically stacked over a substrate, a gate dielectric layer wrapping around the plurality of nanostructures, a gate conductive structure over the gate dielectric layer, and a first insulating spacer alongside the gate conductive structure and over the plurality of nanostructures. The first insulating spacer is in direct contact with the gate conductive structure and the gate dielectric layer.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: June 17, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: I-Sheng Chen, Tzu-Chiang Chen, Cheng-Hsien Wu, Ling-Yen Yeh, Carlos H. Diaz
  • Publication number: 20250194048
    Abstract: A coolant system including one or more cooling fin assemblies that are movably coupled to a coolant tank. Each one of the one or more cooling fin assemblies has a first position (i.e., closed position) in which the one or more cooling fin assemblies are slightly tilted with respect to inner sides of the coolant tank. Each one of the one or more cooling fin assemblies has a second position (i.e., opened position) in which the one or more cooling fin assemblies are tiled by a greater amount than the first position exposing an access opening of the coolant tank such that a transfer device may access a coolant cavity within the coolant tank. Each one of the one or more cooling fin assemblies includes a cooling fin structure and a porous drip tray coupled to the cooling fin structure.
    Type: Application
    Filed: January 5, 2024
    Publication date: June 12, 2025
    Inventors: Tse-Hsien WU, Chyi-Tsong NI, Che-Yu CHIANG
  • Patent number: 12326557
    Abstract: A head-mounted eye tracking system including an eye tracker, a signal processor, and a plurality of light-emitting optical guides is provided. The eye tracker is adaptable for sensing eyeballs of a wearer. The eye tracker includes a plurality of light-emitting devices and a plurality of sensing devices. The plurality of light-emitting devices are adaptable for emitting a tracking beam. The sensing devices are adaptable for receiving the tracking beam reflected by the eyeballs of the wearer. The signal processor is signally connected to the eye tracker. The plurality of light-emitting optical guides is disposed corresponding to the plurality of light-emitting devices.
    Type: Grant
    Filed: October 5, 2023
    Date of Patent: June 10, 2025
    Assignee: Industrial Technology Research Institute
    Inventors: Chia-Hsin Chao, Han-Kuei Fu, Meng-Han Lin, Ming-Hsien Wu
  • Publication number: 20250180641
    Abstract: A detection panel for detecting a light-emitting unit including a substrate and a plurality of detection units is provided. The plurality of detection units are disposed on the substrate, wherein one of the plurality of detection units includes a first detection electrode and a second detection electrode, and there is a first specific distance between the first detection electrode and the second detection electrode. There is a second specific distance between the plurality of detection units and the corresponding light-emitting unit, and the plurality of detection units detect an electrical property generated after the light-emitting unit is illuminated with light to determine whether the light-emitting unit has defects or not. A detection device including the detection panel is also provided.
    Type: Application
    Filed: December 22, 2023
    Publication date: June 5, 2025
    Applicant: Industrial Technology Research Institute
    Inventors: Fu-An Tu, Ming-Hsien Wu
  • Patent number: 12317438
    Abstract: A dust-proof telecommunication system and a method for assembling a dust-proof mechanism are disclosed. The system includes a chassis including an opening on a top side thereof; a PCB located within the chassis; a memory module removably installed on the PCB; and a cover removably coupled to the top side of the chassis. The opening is positioned and shaped such that the memory module is accessible via the opening for easy replacement. The method includes inserting a strip into the opening such that a space is formed between a wall of the opening and the strip; and inserting the memory module into the space formed between the wall of the opening and the strip such that another strip located at a first side of the memory module contacts the wall and the strip contacts a second side of the memory module. The memory module is replaceably coupled to the PCB.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: May 27, 2025
    Assignee: QUANTA COMPUTER INC.
    Inventors: Yaw-Tzorng Tsorng, Tung-Hsien Wu, Yu-Ying Tseng, Hsiang-Pu Ni
  • Patent number: D1083589
    Type: Grant
    Filed: March 28, 2024
    Date of Patent: July 15, 2025
    Assignee: Acer Incorporated
    Inventors: Jhih-Hsien Wu, Chung-Hsien Lee
  • Patent number: D1083600
    Type: Grant
    Filed: April 10, 2024
    Date of Patent: July 15, 2025
    Assignee: Acer Incorporated
    Inventors: Jhih-Hsien Wu, Chung-Hsien Lee