Abstract: A disease diagnosing method and a disease diagnosing system are provided in the disclosure. The disease diagnosing method includes: obtaining continuous images of a body skin and generating a time domain signal according to an average pixel value of a region of interest in each frame of the continuous images; transforming the time domain signal to a frequency domain signal and combining the time domain signal and the frequency domain signal to a time frequency signal; retrieving multiple first features of a first high dimensional space of the time frequency signal to obtain multiple second features of a second high dimensional space; and use the second features as feature vectors to map to a high dimension feature space, and classifying the second features as one of the multiple categories of a disease corresponding to the region of interest in the body skin according to a hyperplane of the high dimension feature space.

Abstract: A Fast Fourier Transform (FFT) processor is provided. It comprises a multiplexer, a first angle rotator, a second angle rotation and multiplexing unit, an adder, a twiddle factor storage, a multiplier, and a data storage. The FFT processor analyzes the input/output order of the Fast Fourier Transformation, separates the portions requiring complex computations, simplifies the hardware thereof, and adjusts the output order. It not only effectively saves the hardware area, but also reduces the computations and memory access count. Thereby, the power consumption is reduced.

Abstract: A prediction device and method for use in a Viterbi decoder is provided. The prediction device is applicable to a communication system with low bit error rate for reducing the count of accessing path memories, thereby lowering the power consumption of the system. The prediction device needs not activate the traceback modules when making a successful prediction. In other words, no access to the path memories is required. The predicted bits decoded and outputted by the decoded bit registers are the decoded bits from the Viterbi decoder. Therefore, the prediction device saves much traceback and power consumption for decoding.

Abstract: A Fast Fourier Transform (FFT) processor is provided. It comprises a multiplexer, a first angle rotator, a second angle rotation and multiplexing unit, an adder, a twiddle factor storage, a multiplier, and a data storage. The FFT processor analyzes the input/output order of the Fast Fourier Transformation, separates the portions requiring complex computations, simplifies the hardware thereof, and adjusts the output order. It not only effectively saves the hardware area, but also reduces the computations and memory access count. Thereby, the power consumption is reduced.

Abstract: A prediction device and method for use in a Viterbi decoder is provided. The prediction device is applicable to a communication system with low bit error rate for reducing the count of accessing path memories, thereby lowering the power consumption of the system. The prediction device needs not activate the traceback modules when making a successful prediction. In other words, no access to the path memories is required. The predicted bits decoded and outputted by the decode bit registers are the decoded bits from the Viterbi decoder. Therefore, the prediction device saves much traceback works and power consumption for decoding.