Abstract: A method of wafer level chip size packaging includes the steps of: grinding a wafer on a back surface to a predetermined thickness; sawing the wafer into a plurality of wafer slices; spray coating a photo resist layer on top of the wafer slice; applying a lithography process to form contact windows on the wafer slice; forming a pattern on the wafer slice by printing or sputtering, in which bottom ends of the pattern are connected with the respective contact windows and an upper surface of the pattern forms protrusively a plurality of under bump metals (UBM); spray coating a solder mask on top of the pattern; applying another lithography process to form apertures on the respective UBMs; implanting solder balls to the respective apertures by printing; and finally sawing the wafer slice into separate dies.