Patents by Inventor Hsin Chang

Hsin Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190338611
    Abstract: The present disclosure provides an automatic push corer system including a base, a power group, a Geneva transmission group, an intermittent transmission group, a vertical coring transmission group, a clamp group and a coring group. The power group is used to drive the Geneva transmission group. The Geneva transmission group is configured to perform a first intermittent rotary motion. The intermittent transmission group is configured to perform a second intermittent rotary motion. The vertical coring transmission group is configured to cooperate with the second intermittent rotary motion to perform a third intermittent rotary motion. The clamp group is configured to cooperate with the third intermittent rotary motion to perform a lifting reciprocation. The coring group is configured to cooperate with the first intermittent rotary motion and the lifting reciprocation to respectively complete a coring operation and a tubing replacing operation.
    Type: Application
    Filed: May 18, 2018
    Publication date: November 7, 2019
    Inventors: YU-CHENG CHOU, HSIN-HUNG CHEN, CHAU-CHANG WANG, BO-SHEN HUANG
  • Publication number: 20190341369
    Abstract: A semiconductor package including an ultra-thin redistribution structure, a semiconductor die, a first insulating encapsulant, a semiconductor chip stack, and a second insulating encapsulant is provided. The semiconductor die is disposed on and electrically coupled to the ultra-thin redistribution structure. The first insulating encapsulant is disposed on the ultra-thin redistribution structure and encapsulates the semiconductor die. The semiconductor chip stack is disposed on the first insulating encapsulant and electrically coupled to the ultra-thin redistribution structure. The second insulating encapsulant is disposed on the ultra-thin redistribution structure and encapsulates the semiconductor chip stack and the first insulating encapsulant. A manufacturing method of a semiconductor package is also provided.
    Type: Application
    Filed: May 2, 2018
    Publication date: November 7, 2019
    Applicant: Powertech Technology Inc.
    Inventors: Shang-Yu Chang Chien, Hung-Hsin Hsu, Nan-Chun Lin
  • Publication number: 20190334495
    Abstract: A sound adjustment method applied to a sound adjustment system is disclosed. The sound adjustment system includes a sound receiving module, a sound identification module, a sound frequency conversion module and a sound equalizer. The sound adjustment method includes the steps of: receiving a sound signal via the sound receiving module; identifying the sound signal via the sound identification module to determine a type of the sound signal; if the sound signal is a voice signal, executing a frequency conversion of the voice signal via the sound frequency conversion module such that the voice signal becomes a frequency-converted voice signal; if the sound signal is a non-voice signal, adjusting the non-voice signal via the sound equalizer such that the non-voice signal becomes an equalizer-adjusted sound signal.
    Type: Application
    Filed: August 14, 2018
    Publication date: October 31, 2019
    Inventors: Kuo-Ping YANG, Ho-Hsin LIAO, Neo Bob Chih-Yung YOUNG, Kuan-Li CHAO, Chih-Long CHANG
  • Publication number: 20190333884
    Abstract: A method of fabricating a contact hole and a fuse hole includes providing a dielectric layer. A conductive pad and a fuse are disposed within the dielectric layer. Then, a first mask is formed to cover the dielectric layer. Later, a first removing process is performed by taking the first mask as a mask to remove part the dielectric layer to form a first trench. The conductive pad is disposed directly under the first trench and does not expose through the first trench. Subsequently, the first mask is removed. After that, a second mask is formed to cover the dielectric layer. Then, a second removing process is performed to remove the dielectric layer directly under the first trench to form a contact hole and to remove the dielectric layer directly above the fuse by taking the second mask as a mask to form a fuse hole.
    Type: Application
    Filed: July 9, 2019
    Publication date: October 31, 2019
    Inventors: Feng-Yi Chang, Fu-Che Lee, Chin-Hsin Chiu
  • Publication number: 20190333836
    Abstract: Semiconductor packages are provided. One of the semiconductor packages includes a first sub-package and a second sub-package. The first sub-package includes a first die, a graphite oxide layer on the first die and an encapsulant encapsulating the first die and the graphite oxide layer. The second sub-package is stacked on and electrically connected to the first sub-package, and includes a second die. The graphite oxide layer is disposed between the first die and the second die.
    Type: Application
    Filed: April 30, 2018
    Publication date: October 31, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Chang Lin, Hsin-Yu Pan, Lipu Kris Chuang, Ming-Chang Lu
  • Patent number: 10461170
    Abstract: A method includes providing a semiconductor structure that includes an epitaxial layer and a cap layer above the epitaxial layer, filling a trench above the cap layer with a sacrificial layer, and removing the sacrificial layer. As such, the cap layer is protected by the sacrificial layer during an etching process and the epitaxial layer is protected by the cap layer during another etching process.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: October 29, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ching-Feng Fu, Yu-Chan Yen, Chih-Hsin Ko, Chun-Hung Lee, Huan-Just Lin, Hui-Cheng Chang
  • Patent number: 10462928
    Abstract: A composite cable assembly includes flat cables, a cable unit and fastening units. Each flat cable includes conductor assemblies and a shielding layer covering the conductor assemblies. The cable unit includes transmission lines. The transmission lines are arranged horizontally and in contact with the shielding layer of the flat cable closest to the transmission lines. The cable unit contacts the flat cable closest to the cable unit, the cable unit and each flat cable are together bent to form bent portions and extension sections connected to the bent portions. Each two fastening units are arranged spaced apart at two sides of a corresponding bent portion. Each extension section has the same length when the cable unit and each flat cable are moved in a movement direction to extend or collapse.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: October 29, 2019
    Assignee: SUPER MICRO COMPUTER INC.
    Inventors: Hsiao-Chung Chen, Tan-Hsin Chang, Chia-Cheng Lu, Chih-Wei Chen
  • Publication number: 20190326256
    Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a first substrate with a first surface and a second surface opposite to the first surface, a second substrate adjacent to the first surface of the first substrate, and an encapsulant encapsulating the first substrate and the second substrate. The first substrate defines a space. The second substrate covers the space. The second surface of the first substrate is exposed by the encapsulant. A surface of the encapsulant is coplanar with the second surface of the first substrate or protrudes beyond the second surface of the first substrate.
    Type: Application
    Filed: April 23, 2018
    Publication date: October 24, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yung-Hsing CHANG, Wen-Hsin LIN
  • Patent number: 10453677
    Abstract: A method of forming an oxide layer includes the following steps. A substrate is provided. A surface of the substrate is treated to form an oxygen ion-rich surface. A spin-on-dielectric layer is formed on the oxygen ion-rich surface of the substrate. The present invention also provides a method of forming an oxide layer including the following steps. A substrate is provided. A surface of the substrate is treated with a hydrogen peroxide (H2O2) solution or a surface of the substrate is treated with oxygen containing gas, to form an oxygen ion-rich surface. A spin-on-dielectric layer is formed on the oxygen ion-rich surface of the substrate.
    Type: Grant
    Filed: July 9, 2017
    Date of Patent: October 22, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Cheng-Hsu Huang, Jui-Min Lee, Ching-Hsiang Chang, Yi-Wei Chen, Wei-Hsin Liu, Shih-Fang Tzou
  • Patent number: 10453995
    Abstract: The present disclosure provides a light-emitting device and manufacturing method thereof. The light-emitting device comprising: a light-emitting stack; and a semiconductor layer having a first surface connecting to the light-emitting stack, a second surface opposite to the first surface, and a void; wherein the void comprises a bottom part near the first surface and an opening on the second surface, and a dimension of the bottom part is larger than the dimension of the opening.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: October 22, 2019
    Assignee: EPISTAR CORPORATION
    Inventors: Wen-Luh Liao, Chih-Chiang Lu, Shih-Chang Lee, Hung-Ta Cheng, Hsin-Chan Chung, Yi-Chieh Lin
  • Publication number: 20190318967
    Abstract: Generally, the present disclosure provides example embodiments relating to tuning threshold voltages in transistor devices and the transistor devices formed thereby. Various examples implementing various mechanisms for tuning threshold voltages are described. In an example method, a gate dielectric layer is deposited over an active area in a device region of a substrate. A dipole layer is deposited over the gate dielectric layer in the device region. A dipole dopant species is diffused from the dipole layer into the gate dielectric layer in the device region.
    Type: Application
    Filed: April 13, 2018
    Publication date: October 17, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zoe Chen, Ching-Hwanq Su, Cheng-Lung Hung, Cheng-Yen Tsai, Da-Yuan Lee, Hsin-Yi Lee, Weng Chang, Wei-Chin Lee
  • Patent number: 10439077
    Abstract: The instant disclosure provides an optical component packaging structure which includes a far-infrared sensor chip, a first metal layer, a packaging housing and a covering member. The far-infrared sensor chip includes a semiconductor substrate and a semiconductor stack structure. The semiconductor substrate has a first surface, a second surface which is opposite to the first surface, and a cavity. The semiconductor stack structure is disposed on the first surface of the semiconductor substrate, and a part of the semiconductor stack structure is located above the cavity. The first metal layer is disposed on the second surface of the semiconductor substrate, the packaging housing is used to encapsulate the far-infrared sensor chip and expose at least a part of the far-infrared sensor chip, and the covering member is disposed above the semiconductor stack structure.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: October 8, 2019
    Assignee: PIXART IMAGING INC.
    Inventors: Yi-Chang Chang, Yen-Hsin Chen, Chi-Chih Shen
  • Patent number: 10437289
    Abstract: A button installed on a housing of an electronic device includes a keycap, a button frame, a waterproofing ring, and at least one installation post. The button frame is latched with the keycap and defines at least one through hole. The waterproofing ring is disposed within the at least one through hole. At least one installation post is received through the waterproofing ring and resists against the keycap.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: October 8, 2019
    Assignee: Chiun Mai Communication Systems, Inc.
    Inventors: Chia-Hsin Chang, Shih-Kuo Tsai
  • Patent number: 10438931
    Abstract: A package structure includes a first redistribution layer, a second redistribution layer, a die, a plurality of conductive pillars and a die-stacked structure. The first redistribution layer has a first surface and a second surface opposite to the first surface. The second redistribution layer is disposed above the first surface. The die is disposed between the first redistribution layer and the second redistribution layer and has an active surface and a rear surface opposite to the active surface. The active surface is adhered to the first surface, and the die is electrically connected to the first redistribution layer. The conductive pillars are disposed and electrically connected between the first redistribution layer and the second redistribution layer. The die-stacked structure is bonded on the second redistribution layer.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: October 8, 2019
    Assignee: Powertech Technology Inc.
    Inventors: Han-Wen Lin, Hung-Hsin Hsu, Shang-Yu Chang Chien, Nan-Chun Lin
  • Publication number: 20190300224
    Abstract: A packaging box includes a bottom plate, two cover plates, two external plates, two internal plates, and four flaps. Each of the flaps has an engaging opening. When the packaging box is formed, the four flaps are respectively folded to closely contact the corresponding external plates, and the two internal plates are respectively folded to be inserted into the engaging openings of the two flaps on the corresponding sides, to save materials of the packaging box.
    Type: Application
    Filed: February 15, 2019
    Publication date: October 3, 2019
    Inventors: Xiao-Song JIANG, Yu-Cai JIANG, Hsin-Chang LU
  • Publication number: 20190304924
    Abstract: A high voltage (HV) converter implemented on a printed circuit board (PCB) includes a double diffused metal oxide semiconductor (DMOS) package comprising a lead frame and a main DMOS chip. The lead frame includes a gate section electrically connected to a gate electrode of the main DMOS chip, a source section electrically connected to a source electrode of the main DMOS chip and a drain section electrically connected to a drain electrode of the main DMOS chip. The PCB layout includes a large area source copper pad attached to and overlapping the source section of the DMOS package to facilitate cooling and a small area drain copper pad attached to and overlapping the drain section of the DMOS package to reduce electromagnetic interference (EMI) noise.
    Type: Application
    Filed: March 29, 2018
    Publication date: October 3, 2019
    Applicant: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Zhiqiang Niu, Kuang Ming Chang, Lin Chen, Ning Sun, QiHong Huang, Tzu-Hsin Lu
  • Patent number: 10432007
    Abstract: Circuits, systems and methods that may be implemented to achieve thermal management for system load components by balancing power between multiple input power current paths for a narrow voltage DC (NVDC) circuit architecture coupled to receive input external DC power, e.g., such as provided by an external AC adapter. At least one of the multiple current paths may be coupled to supply DC power to a lower voltage portion of a system load through a charger circuit, while at least one other of the multiple current paths may be coupled to selectably supply DC power directly to another and different higher voltage portion of the system load, bypassing the charger circuit and related NVDC components.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: October 1, 2019
    Assignee: Dell Products L.P.
    Inventors: Chen-Hsin Chang, Chih-Chiang Tsui
  • Patent number: 10432709
    Abstract: The disclosure provides a load balancing method, a load balancing system, a load balancing device and a topology reduction method. The load balancing method includes configuring a transmission progress value for each of the edge servers; grouping the edge servers into server groups, wherein each of the edge servers is grouped into at least one server group among the server groups; receiving a download request corresponding to a first video stream from a user device, wherein a first server group among the server groups provides the first video stream; and selecting one of the edge servers from the edge servers of the first server group as a first edge server to provide video data of the first video stream to the user device according to the transmission progress values of the edge servers of the first server group.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: October 1, 2019
    Assignee: Industrial Technology Research Institute
    Inventors: Shu-Hsin Chang, Kun-Hsien Lu, Yu-Hsien Hsiao, Ching-Chun Kao, Yi-Yu Su
  • Publication number: 20190297707
    Abstract: An intelligent lamp holder includes a microprocessor, an acoustic reception and transmission element, a sound recognition module, a light modulation module and a sensing module. The acoustic reception and transmission element is connected with an external ultrasonic device for receiving ultrasonic signals, and the acoustic reception and transmission element converts the ultrasonic signals into digital signals. The sound recognition module is connected with and controlled by the microprocessor, and the sound recognition module is connected with the acoustic reception and transmission element. The digital signals are transmitted to the sound recognition module. The sound recognition module receives and recognizes the digital signals to generate execution instructions. The light modulation module is connected with and controlled by the microprocessor for controlling on-off statuses and a brightness modulation of a lamp according to different execution instructions.
    Type: Application
    Filed: February 27, 2019
    Publication date: September 26, 2019
    Inventors: James Cheng Lee, Kuo Yang Wu, Wen Bing Hsu, Hsin Chang Chen
  • Publication number: 20190296645
    Abstract: A circuit assembly for a power converter includes power stage blocks and heat-dissipating substrate. A power stage block includes a power stage IC die, an output inductor that is connected to a switch node of the power stage IC die, and capacitors that form an output capacitor of the power stage block. The output capacitors of the power stage blocks are symmetrically arranged. The output inductors can be placed on the same side of the substrate as the power stage IC dies, or on a side of the substrate that is opposite to the side where the power stage IC dies are disposed. A power stage block may generate two output phases of the power converter.
    Type: Application
    Filed: June 11, 2019
    Publication date: September 26, 2019
    Applicant: Monolithic Power Systems, Inc.
    Inventors: Jinghai ZHOU, Chia-Hsin CHANG